From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JA5Wh-0005kL-J8 for qemu-devel@nongnu.org; Wed, 02 Jan 2008 10:29:03 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JA5Wg-0005jb-Qm for qemu-devel@nongnu.org; Wed, 02 Jan 2008 10:29:03 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JA5Wg-0005jN-Lo for qemu-devel@nongnu.org; Wed, 02 Jan 2008 10:29:02 -0500 Received: from main.gmane.org ([80.91.229.2] helo=ciao.gmane.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JA5Wg-0002MF-DV for qemu-devel@nongnu.org; Wed, 02 Jan 2008 10:29:02 -0500 Received: from list by ciao.gmane.org with local (Exim 4.43) id 1JA5WY-000213-PW for qemu-devel@nongnu.org; Wed, 02 Jan 2008 15:28:56 +0000 Received: from mtvcafw.sgi.com ([192.48.171.6]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 02 Jan 2008 15:28:54 +0000 Received: from bjj4 by mtvcafw.sgi.com with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 02 Jan 2008 15:28:54 +0000 From: Brian Johnson Date: Wed, 02 Jan 2008 09:28:49 -0600 Message-ID: <477BADB1.30400@charter.net> References: <477B0507.90707@earthlink.net> <200801021401.13611.paul@codesourcery.com> <477BA5AB.6030406@earthlink.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit In-Reply-To: <477BA5AB.6030406@earthlink.net> Sender: news Subject: [Qemu-devel] Re: [RFC] 64 bit i/o Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Robert Reif wrote: > Paul Brook wrote: >> >> Couldn't you just latch the value when one half is accessed? >> > In this one specific case you could do that but this is not the only > case in sparc32 (TOD, MXCC, ...) and other architectures with 64 bit > hardware have similar requirements. > > This is a generic solution that fills a hole in the qemu > implementation. Agreed. Some non-PC hardware has 64-bit registers which need to be accessed as 64-bit quantities, in order to read or write all fields at once. Qemu should support 64-bit I/O. Brian