From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JCG6j-0007v8-4F for qemu-devel@nongnu.org; Tue, 08 Jan 2008 10:11:13 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JCG6i-0007uE-C1 for qemu-devel@nongnu.org; Tue, 08 Jan 2008 10:11:12 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JCG6i-0007tq-4s for qemu-devel@nongnu.org; Tue, 08 Jan 2008 10:11:12 -0500 Received: from kassel160.server4you.de ([62.75.246.160] helo=csgraf.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JCG6h-0007nU-LC for qemu-devel@nongnu.org; Tue, 08 Jan 2008 10:11:11 -0500 Received: from [10.10.102.8] (charybdis-ext.suse.de [195.135.221.2]) by csgraf.de (Postfix) with ESMTP id 811523A8A for ; Tue, 8 Jan 2008 16:11:10 +0100 (CET) Message-ID: <4783954E.7030302@csgraf.de> Date: Tue, 08 Jan 2008 16:22:54 +0100 From: Alexander Graf MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------000100060106090605040101" Subject: [Qemu-devel] [PATCH 6/9] ICH-6 IDE controller Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------000100060106090605040101 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit The oldest supported IDE controller in Mac OS X is the ICH6. This is an incomplete implementation for that controller, that suffices for running Mac OS X and worked with libata for me as well. --------------000100060106090605040101 Content-Type: text/x-patch; name="qemu-ide.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="qemu-ide.patch" Index: qemu-snapshot-2008-01-08_05/hw/ide.c =================================================================== --- qemu-snapshot-2008-01-08_05.orig/hw/ide.c +++ qemu-snapshot-2008-01-08_05/hw/ide.c @@ -386,6 +386,7 @@ typedef struct IDEState { #define IDE_TYPE_PIIX3 0 #define IDE_TYPE_CMD646 1 #define IDE_TYPE_PIIX4 2 +#define IDE_TYPE_ICH6 3 /* CMD646 specific */ #define MRDMODE 0x71 @@ -2934,7 +2935,7 @@ static void piix3_reset(PCIIDEState *d) { uint8_t *pci_conf = d->dev.config; - pci_conf[0x04] = 0x00; + pci_conf[0x04] = 0x01; pci_conf[0x05] = 0x00; pci_conf[0x06] = 0x80; /* FBC */ pci_conf[0x07] = 0x02; // PCI_status_devsel_medium @@ -2961,11 +2962,68 @@ void pci_piix3_ide_init(PCIBus *bus, Blo pci_conf[0x01] = 0x80; pci_conf[0x02] = 0x10; pci_conf[0x03] = 0x70; + +// ICH-6: 0x269e8086 + pci_conf[0x00] = 0x86; // Intel + pci_conf[0x01] = 0x80; + //pci_conf[0x02] = 0x9e;// 11; + //pci_conf[0x03] = 0x26;//71; + + pci_conf[0x09] = 0x80; // legacy ATA mode + pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE + pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage + pci_conf[0x0e] = 0x00; // header_type + + pci_conf[0x40] = 0; + pci_conf[0x41] = 0xf0; // primary port enabled + pci_conf[0x42] = 0; + pci_conf[0x43] = 0x00; // secondary port disabled + + piix3_reset(d); + + pci_register_io_region((PCIDevice *)d, 4, 0x10, + PCI_ADDRESS_SPACE_IO, bmdma_map); + + ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]); + ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]); + ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); + ide_init_ioport(&d->ide_if[2], 0x170, 0x376); + + register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); +} + +/* hd_table must contain 4 block drivers */ +/* NOTE: for the ICH-6, the IRQs and IOports are hardcoded */ +void pci_ich6_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, + qemu_irq *pic) +{ + PCIIDEState *d; + uint8_t *pci_conf; + + /* register a function 1 of ICH-6 */ + d = (PCIIDEState *)pci_register_device(bus, "ICH-6 IDE", + sizeof(PCIIDEState), + devfn, + NULL, NULL); + d->type = IDE_TYPE_ICH6; + + pci_conf = d->dev.config; + pci_conf[0x00] = 0x86; // Intel + pci_conf[0x01] = 0x80; + pci_conf[0x02] = 0x9e; + pci_conf[0x03] = 0x26; + pci_conf[0x09] = 0x80; // legacy ATA mode pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage pci_conf[0x0e] = 0x00; // header_type + pci_conf[0x40] = 0; + pci_conf[0x41] = 0xf0; // primary port enabled + pci_conf[0x42] = 0; + pci_conf[0x43] = 0x00; // secondary port disabled + + //pci_conf[0x21] = 0xef; /* BMIBA: 20-23h */ piix3_reset(d); pci_register_io_region((PCIDevice *)d, 4, 0x10, Index: qemu-snapshot-2008-01-08_05/hw/pc.h =================================================================== --- qemu-snapshot-2008-01-08_05.orig/hw/pc.h +++ qemu-snapshot-2008-01-08_05/hw/pc.h @@ -137,6 +137,8 @@ void pci_piix3_ide_init(PCIBus *bus, Blo qemu_irq *pic); void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, qemu_irq *pic); +void pci_ich6_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, + qemu_irq *pic); /* ne2000.c */ --------------000100060106090605040101--