From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JFX2N-0002w5-V5 for qemu-devel@nongnu.org; Thu, 17 Jan 2008 10:52:16 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JFX2H-0002so-DT for qemu-devel@nongnu.org; Thu, 17 Jan 2008 10:52:14 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JFX2G-0002sk-Nl for qemu-devel@nongnu.org; Thu, 17 Jan 2008 10:52:08 -0500 Received: from kassel160.server4you.de ([62.75.246.160] helo=csgraf.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JFX2F-0005Uw-Pf for qemu-devel@nongnu.org; Thu, 17 Jan 2008 10:52:08 -0500 Received: from [10.10.103.17] (charybdis-ext.suse.de [195.135.221.2]) by csgraf.de (Postfix) with ESMTP id 37A1B2D32 for ; Thu, 17 Jan 2008 16:52:03 +0100 (CET) Message-ID: <478F79A3.3020108@csgraf.de> Date: Thu, 17 Jan 2008 16:52:03 +0100 From: Alexander Graf MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH]SVM CR8 undefined bug fix References: <14921864.post@talk.nabble.com> In-Reply-To: <14921864.post@talk.nabble.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org TeLeMan wrote: > env->cr[8] used by SVM codes was not defined. > > As far as I remember cr8 is the very same as the TPR, so we only need to implement one and map the other to the value we want. My approach was to use the TPR and route the cr8 accesses to the tpr. Even though I have to admit that this might not be consistent throughout the code right now. > http://www.nabble.com/file/p14921864/svm_cr8.patch svm_cr8.patch: > > diff -p -u qemu.orig/target-i386/cpu.h qemu/target-i386/cpu.h > --- qemu.orig/target-i386/cpu.h Mon Jan 14 11:11:08 2008 > +++ qemu/target-i386/cpu.h Thu Jan 17 23:21:22 2008 > @@ -493,7 +493,7 @@ typedef struct CPUX86State { > SegmentCache gdt; /* only base and limit are used */ > SegmentCache idt; /* only base and limit are used */ > > - target_ulong cr[5]; /* NOTE: cr1 is unused */ > + target_ulong cr[9]; /* NOTE: cr1,cr5-cr7 are unused */ > uint32_t a20_mask; > > /* FPU state */ > diff -p -u qemu.orig/target-i386/helper.c qemu/target-i386/helper.c > --- qemu.orig/target-i386/helper.c Mon Jan 14 11:11:08 2008 > +++ qemu/target-i386/helper.c Thu Jan 17 23:24:04 2008 > @@ -2718,6 +2718,7 @@ void helper_movl_crN_T0(int reg) > break; > case 8: > cpu_set_apic_tpr(env, T0); > + env->cr[8] = T0; > break; > default: > env->cr[reg] = T0; > @@ -4065,6 +4066,7 @@ void helper_vmrun(target_ulong addr) > int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, > control.int_ctl)); > if (int_ctl & V_INTR_MASKING_MASK) { > env->cr[8] = int_ctl & V_TPR_MASK; > + cpu_set_apic_tpr(env,env->cr[8]); > This is a valid catch. > if (env->eflags & IF_MASK) > env->hflags |= HF_HIF_MASK; > } > @@ -4376,8 +4378,10 @@ void vmexit(uint64_t exit_code, uint64_t > cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, > save.cr0)) | CR0_PE_MASK); > cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, > save.cr4))); > cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, > save.cr3))); > - if (int_ctl & V_INTR_MASKING_MASK) > + if (int_ctl & V_INTR_MASKING_MASK) { > env->cr[8] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, > This too. > save.cr8)); > + cpu_set_apic_tpr(env,env->cr[8]); > + } > /* we need to set the efer after the crs so the hidden flags get set > properly */ > #ifdef TARGET_X86_64 > env->efer = ldq_phys(env->vm_hsave + offsetof(struct vmcb, > save.efer)); > >