From: Richard Henderson <richard.henderson@linaro.org>
To: "Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
qemu-devel@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Gregory Price" <gregory.price@memverge.com>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: linux-cxl@vger.kernel.org, linuxarm@huawei.com
Subject: Re: [PATCH v3] arm/ptw: Handle atomic updates of page tables entries in MMIO during PTW.
Date: Fri, 23 Feb 2024 08:19:55 -1000 [thread overview]
Message-ID: <47974032-2c22-481c-a9e1-1fc5990340d6@linaro.org> (raw)
In-Reply-To: <20240223180102.7657-1-Jonathan.Cameron@huawei.com>
On 2/23/24 08:01, Jonathan Cameron wrote:
> Seen testing of CXL emulation on arm64 (currently out of tree).
>
> CXL interleave occurs at subpage granularity so is emulated using an IO
> Memory Region. The memory is general purpose and as such may contain page
> tables. FEAT_HADFS using atomic accesses from the page table walkers to
> update accessed and dirty bits.
>
> Note that disabling kernel support this ARM 8.1 feature avoids this issue
> as the PTW no longer does an atomic update of the page table entries, but
> that is a nasty workaround beyond its use in root causing this issue.
>
> Signed-off-by: Jonathan Cameron<Jonathan.Cameron@huawei.com>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-02-23 18:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 18:01 [PATCH v3] arm/ptw: Handle atomic updates of page tables entries in MMIO during PTW Jonathan Cameron via
2024-02-23 18:19 ` Richard Henderson [this message]
2024-02-26 14:12 ` Peter Maydell
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