From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JHgJG-0004VG-Pe for qemu-devel@nongnu.org; Wed, 23 Jan 2008 09:10:34 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JHgJF-0004TR-Mk for qemu-devel@nongnu.org; Wed, 23 Jan 2008 09:10:34 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JHgJF-0004TA-HM for qemu-devel@nongnu.org; Wed, 23 Jan 2008 09:10:33 -0500 Received: from pop-gadwall.atl.sa.earthlink.net ([207.69.195.61]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1JHgJF-00066h-8g for qemu-devel@nongnu.org; Wed, 23 Jan 2008 09:10:33 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-gadwall.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1JHgJC-0002pQ-00 for qemu-devel@nongnu.org; Wed, 23 Jan 2008 09:10:30 -0500 Message-ID: <47974AD7.8000000@earthlink.net> Date: Wed, 23 Jan 2008 09:10:31 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------000001060506060603040601" Subject: [Qemu-devel] [PATCH] hs/iommu.c add turboSPARC mask id register Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------000001060506060603040601 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Add microSPARC II and turboSPARC mask ID register support. --------------000001060506060603040601 Content-Type: text/plain; name="iommu.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="iommu.diff.txt" Index: hw/iommu.c =================================================================== RCS file: /sources/qemu/qemu/hw/iommu.c,v retrieving revision 1.25 diff -p -u -r1.25 iommu.c --- hw/iommu.c 1 Jan 2008 17:06:38 -0000 1.25 +++ hw/iommu.c 23 Jan 2008 14:06:26 -0000 @@ -34,7 +34,7 @@ do { printf("IOMMU: " fmt , ##args); } w #define DPRINTF(fmt, args...) #endif -#define IOMMU_NREGS (3*4096/4) +#define IOMMU_NREGS (4*4096/4) #define IOMMU_CTRL (0x0000 >> 2) #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ @@ -95,6 +95,12 @@ do { printf("IOMMU: " fmt , ##args); } w #define IOMMU_ARBEN_MASK 0x001f0000 #define IOMMU_MID 0x00000008 +#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ +#define IOMMU_MASK_ID_MASK 0x00ffffff + +#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ +#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ + /* The format of an iopte in the page tables */ #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or @@ -206,6 +212,9 @@ static void iommu_mem_writel(void *opaqu // addresses, fault cause and address stored to MMU/IOMMU s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; break; + case IOMMU_MASK_ID: + s->regs[saddr] |= (val & IOMMU_MASK_ID_MASK); + break; default: s->regs[saddr] = val; break; @@ -337,6 +346,7 @@ static void iommu_reset(void *opaque) s->regs[IOMMU_CTRL] = s->version; s->regs[IOMMU_ARBEN] = IOMMU_MID; s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; + s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; qemu_irq_lower(s->irq); } --------------000001060506060603040601--