From: Fabrice Bellard <fabrice@bellard.org>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>
Subject: [Qemu-devel] Re: [PATCH, RFC, WIP] TCG for Qemu target Sparc32/64
Date: Sat, 23 Feb 2008 19:23:49 +0100 [thread overview]
Message-ID: <47C064B5.4040809@bellard.org> (raw)
In-Reply-To: <f43fc5580802211227u4e6e5ee6ofd4582c3a16bce46@mail.gmail.com>
Blue Swirl wrote:
> The attached patch enables most TCG ops for Qemu Sparc32/64 target.
> Sparc32 softmmu and linux-user are OK, but Sparc64 and Sparc32plus
> targets do not work.
>
> Comments?
>
> It would be nice to get rid of T2 usage in std (also stda and
> casa/casxa) but I don't know how to pass a 64-bit value from legacy op
> to TCG stores and loads on a 32-bit target and host.
[...]
Also don't forget that T2 is used in CPU restore state to handle delay
slots. This part of the SPARC target is tricky and should be simplified.
Another point is that you should define TCG globals for each SPARC GPR.
It was not done for i386 because I feared performance regressions when
accessing to 16 bit or 8 bit sub-registers. On SPARC you do not have
this issue.
Regarding the generic "xxx_tl" defines, I did not move it into TCG
because I wanted TCG to be target independent. Since it is no longer the
case because of the target memory access instructions, I think it is a
good idea now. But do not mix the target specific defines with target
independent defines (in tcg-op.h there is a specific section for target
specific defines).
Regards,
Fabrice.
next prev parent reply other threads:[~2008-02-23 18:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-02-21 20:27 [Qemu-devel] [PATCH, RFC, WIP] TCG for Qemu target Sparc32/64 Blue Swirl
2008-02-22 0:06 ` Thiemo Seufer
2008-02-22 16:13 ` Blue Swirl
2008-02-23 18:23 ` Fabrice Bellard [this message]
2008-02-23 18:29 ` [Qemu-devel] " Blue Swirl
2008-02-23 18:48 ` Fabrice Bellard
2008-02-23 20:32 ` Paul Brook
2008-02-23 23:59 ` Stuart Brady
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