From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JSzRA-0006G8-Fk for qemu-devel@nongnu.org; Sat, 23 Feb 2008 13:49:28 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JSzR8-0006FI-DH for qemu-devel@nongnu.org; Sat, 23 Feb 2008 13:49:28 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JSzR8-0006FF-A0 for qemu-devel@nongnu.org; Sat, 23 Feb 2008 13:49:26 -0500 Received: from relay4-v.mail.gandi.net ([217.70.178.78]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1JSzR7-0007Bv-Ly for qemu-devel@nongnu.org; Sat, 23 Feb 2008 13:49:26 -0500 Message-ID: <47C06A86.6040003@bellard.org> Date: Sat, 23 Feb 2008 19:48:38 +0100 From: Fabrice Bellard MIME-Version: 1.0 References: <47C064B5.4040809@bellard.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: [PATCH, RFC, WIP] TCG for Qemu target Sparc32/64 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org > [...] >> Another point is that you should define TCG globals for each SPARC GPR. >> It was not done for i386 because I feared performance regressions when >> accessing to 16 bit or 8 bit sub-registers. On SPARC you do not have >> this issue. > > Nice idea. Would this also work for windowed registers? Yes, provided you use a fixed register to store regwptr. Then you can define the windowed registers as globals using this register as base. The real problem is to save and restore this register in cpu_exec() and in all the places where the regwptr CPU state field is accessed directly. TCG will handle these problems generically soon, but before it does it you can implement it "by hand". Regards, Fabrice.