From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JU7ww-0006NR-IO for qemu-devel@nongnu.org; Tue, 26 Feb 2008 17:06:58 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JU7wt-0006ND-Rl for qemu-devel@nongnu.org; Tue, 26 Feb 2008 17:06:57 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JU7wt-0006NA-N4 for qemu-devel@nongnu.org; Tue, 26 Feb 2008 17:06:55 -0500 Received: from slow2-v.mail.gandi.net ([217.70.178.89]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1JU7wt-0005Jr-A8 for qemu-devel@nongnu.org; Tue, 26 Feb 2008 17:06:55 -0500 Received: from relay3-v.mail.gandi.net (relay3-v.mail.gandi.net [217.70.178.77]) by slow2-v.mail.gandi.net (Postfix) with ESMTP id 81B6621CE53 for ; Tue, 26 Feb 2008 23:06:54 +0100 (CET) Message-ID: <47C48D3B.8040208@bellard.org> Date: Tue, 26 Feb 2008 23:05:47 +0100 From: Fabrice Bellard MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: TCG on i386 can't generate qemu_st64 for 32-bit target Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org Blue Swirl wrote: > Hi, > > There is a problem with the Sparc32 target on i386 host. Store double > word op (std) cannot be generated and TCG just aborts. It looks like > the registers are so few on i386 that TCG can't find registers for the > qemu_st64 call. The problem does not appear on x86_64 host, or for > Sparc64 target (stx/ldx) on i386, or with 64-bit load (ldd) on Sparc32 > target. > > The attached patch would work around the problem, but I agree that > it's ugly and it would bring back one instance of T2 use. I also tried > preallocating a 64-bit register but that didn't help. > > I suppose instead the following piece (tcg/i386/tcg-target.c:737) > could be modified to lower the pressure for registers but I'm not that > familiar with x86 assembly. > [...] There are not enough free registers because of the legacy 3 cpu_T[n] fixed registers. Once you have no helpers using cpu_T[n] implicitely, it will be possible to allocate cpu_T[n] as normal temporaries and to free the associated fixed registers. Before that your solution is acceptable. Another hack would be to force the 'r_dword' variable to be stored in cpu_T[1] and cpu_T[2], but TCG gives no clean way to do it. Fabrice.