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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e0cd2c90sm12240625e9.17.2025.08.04.15.56.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Aug 2025 15:56:07 -0700 (PDT) Message-ID: <47ba48ae-e3d6-47a0-9aa4-35c0a14d7c9f@linaro.org> Date: Tue, 5 Aug 2025 00:56:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 09/17] whpx: add arm64 support To: Mohamed Mediouni , qemu-devel@nongnu.org Cc: Shannon Zhao , Ani Sinha , Phil Dennis-Jordan , Roman Bolshakov , Igor Mammedov , Eduardo Habkost , Mads Ynddal , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Sunil Muthuswamy , Zhao Liu , "Michael S. Tsirkin" , Alexander Graf , qemu-arm@nongnu.org, Peter Maydell , Marcel Apfelbaum , Yanan Wang , Richard Henderson , Cameron Esfahani , Paolo Bonzini , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= References: <20250804142326.72947-1-mohamed@unpredictable.fr> <20250804142326.72947-10-mohamed@unpredictable.fr> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250804142326.72947-10-mohamed@unpredictable.fr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/8/25 16:23, Mohamed Mediouni wrote: > Signed-off-by: Mohamed Mediouni > --- > accel/whpx/whpx-common.c | 1 + > meson.build | 21 +- > target/arm/meson.build | 1 + > target/arm/whpx/meson.build | 3 + > target/arm/whpx/whpx-all.c | 845 ++++++++++++++++++++++++++++++++++++ > 5 files changed, 864 insertions(+), 7 deletions(-) > create mode 100644 target/arm/whpx/meson.build > create mode 100644 target/arm/whpx/whpx-all.c > +int whpx_init_vcpu(CPUState *cpu) > +{ > + HRESULT hr; > + struct whpx_state *whpx = &whpx_global; > + AccelCPUState *vcpu = NULL; > + ARMCPU *arm_cpu = ARM_CPU(cpu); > + CPUARMState *env = &arm_cpu->env; > + int ret; > + > + uint32_t sregs_match_len = ARRAY_SIZE(whpx_sreg_match); > + uint32_t sregs_cnt = 0; > + WHV_REGISTER_VALUE val; > + int i; > + > + vcpu = g_new0(AccelCPUState, 1); > + > + hr = whp_dispatch.WHvCreateVirtualProcessor( > + whpx->partition, cpu->cpu_index, 0); > + if (FAILED(hr)) { > + error_report("WHPX: Failed to create a virtual processor," > + " hr=%08lx", hr); > + ret = -EINVAL; > + goto error; > + } > + > + /* Assumption that CNTFRQ_EL0 is the same between the VMM and the partition. */ > + asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); > + > + cpu->vcpu_dirty = true; > + cpu->accel = vcpu; > + max_vcpu_index = max(max_vcpu_index, cpu->cpu_index); > + qemu_add_vm_change_state_handler(whpx_cpu_update_state, env); > + > + env->aarch64 = true; > + > + /* Allocate enough space for our sysreg sync */ > + arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, > + sregs_match_len); > + arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, > + sregs_match_len); > + arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, > + arm_cpu->cpreg_vmstate_indexes, > + sregs_match_len); > + arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, > + arm_cpu->cpreg_vmstate_values, > + sregs_match_len); > + > + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); > + > + /* Populate cp list for all known sysregs */ > + for (i = 0; i < sregs_match_len; i++) { > + const ARMCPRegInfo *ri; > + uint32_t key = whpx_sreg_match[i].key; > + > + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); > + if (ri) { > + assert(!(ri->type & ARM_CP_NO_RAW)); > + whpx_sreg_match[i].cp_idx = sregs_cnt; > + arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); > + } else { > + whpx_sreg_match[i].cp_idx = -1; > + } > + } > + arm_cpu->cpreg_array_len = sregs_cnt; > + arm_cpu->cpreg_vmstate_array_len = sregs_cnt; > + > + assert(write_cpustate_to_list(arm_cpu, false)); > + > + /* Set CP_NO_RAW system registers on init */ > + val.Reg64 = arm_cpu->midr; > + whpx_set_reg(cpu, WHvArm64RegisterMidrEl1, > + val); > + > + clean_whv_register_value(&val); > + > + /* bit 31 of MPIDR_EL1 is RES1, and this is enforced by WHPX */ > + val.Reg64 = 0x80000000 + arm_cpu->mp_affinity; Preferably: val.Reg64 = deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); > + whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, > + val); (note, your indentation is often off) > + > + return 0; > + > +error: > + g_free(vcpu); > + > + return ret; > + > +}