From: Richard Henderson <richard.henderson@linaro.org>
To: Song Gao <gaosong@loongson.cn>, qemu-devel@nongnu.org
Subject: Re: [PATCH v1 04/46] target/loongarch: Implement xvadd/xvsub
Date: Tue, 20 Jun 2023 14:25:20 +0200 [thread overview]
Message-ID: <47d12e8b-493a-e58c-54a1-47bd919c7e20@linaro.org> (raw)
In-Reply-To: <20230620093814.123650-5-gaosong@loongson.cn>
On 6/20/23 11:37, Song Gao wrote:
> +static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop,
> + void (*func)(unsigned, uint32_t, uint32_t,
> + uint32_t, uint32_t, uint32_t))
> +{
> + uint32_t xd_ofs, xj_ofs, xk_ofs;
> +
> + CHECK_ASXE;
> +
> + xd_ofs = vec_full_offset(a->xd);
> + xj_ofs = vec_full_offset(a->xj);
> + xk_ofs = vec_full_offset(a->xk);
> +
> + func(mop, xd_ofs, xj_ofs, xk_ofs, 32, ctx->vl / 8);
> + return true;
> +}
Comparing gvec_xxx vs gvec_vvv for LSX,
> func(mop, vd_ofs, vj_ofs, vk_ofs, 16, ctx->vl/8);
gvec_vvv will write 16 bytes of output, followed by 16 bytes of zero to satisfy vl / 8.
I presume this is the intended behaviour of mixing LSX with LASX, that the high 128-bits
that are not considered by the LSX instruction are zeroed on write?
Which means that your macros from patch 1,
> +#if HOST_BIG_ENDIAN
...
> +#define XB(x) XB[31 - (x)]
> +#define XH(x) XH[15 - (x)]
are incorrect. We need big-endian within the Int128, but little-endian ordering of the
two Int128. This can be done with
#define XB(x) XB[(x) ^ 15]
#define XH(x) XH[(x) ^ 7]
etc.
It would be nice to share more code with trans_lsx.c, if possible.
r~
next prev parent reply other threads:[~2023-06-20 12:25 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-20 9:37 [PATCH v1 00/46] Add LoongArch LASX instructions Song Gao
2023-06-20 9:37 ` [PATCH v1 01/46] target/loongarch: Add LASX data type XReg Song Gao
2023-06-20 12:09 ` Richard Henderson
2023-06-21 9:19 ` Song Gao
2023-06-20 9:37 ` [PATCH v1 02/46] target/loongarch: meson.build support build LASX Song Gao
2023-06-20 9:37 ` [PATCH v1 03/46] target/loongarch: Add CHECK_ASXE maccro for check LASX enable Song Gao
2023-06-20 12:10 ` Richard Henderson
2023-06-20 9:37 ` [PATCH v1 04/46] target/loongarch: Implement xvadd/xvsub Song Gao
2023-06-20 12:25 ` Richard Henderson [this message]
2023-06-21 9:19 ` Song Gao
2023-06-21 9:27 ` Richard Henderson
2023-06-21 9:56 ` Song Gao
2023-06-20 9:37 ` [PATCH v1 05/46] target/loongarch: Implement xvreplgr2vr Song Gao
2023-06-20 9:37 ` [PATCH v1 06/46] target/loongarch: Implement xvaddi/xvsubi Song Gao
2023-06-20 9:37 ` [PATCH v1 07/46] target/loongarch: Implement xvneg Song Gao
2023-06-20 9:37 ` [PATCH v1 08/46] target/loongarch: Implement xvsadd/xvssub Song Gao
2023-06-20 9:37 ` [PATCH v1 09/46] target/loongarch: Implement xvhaddw/xvhsubw Song Gao
2023-06-20 9:37 ` [PATCH v1 10/46] target/loongarch: Implement xvaddw/xvsubw Song Gao
2023-06-20 9:37 ` [PATCH v1 11/46] target/loongarch: Implement xavg/xvagr Song Gao
2023-06-20 9:37 ` [PATCH v1 12/46] target/loongarch: Implement xvabsd Song Gao
2023-06-20 9:37 ` [PATCH v1 13/46] target/loongarch: Implement xvadda Song Gao
2023-06-20 9:37 ` [PATCH v1 14/46] target/loongarch: Implement xvmax/xvmin Song Gao
2023-06-20 9:37 ` [PATCH v1 15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od} Song Gao
2023-06-20 9:37 ` [PATCH v1 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od} Song Gao
2023-06-20 9:37 ` [PATCH v1 17/46] target/loongarch; Implement xvdiv/xvmod Song Gao
2023-06-20 9:37 ` [PATCH v1 18/46] target/loongarch: Implement xvsat Song Gao
2023-06-20 9:37 ` [PATCH v1 19/46] target/loongarch: Implement xvexth Song Gao
2023-06-20 9:37 ` [PATCH v1 20/46] target/loongarch: Implement vext2xv Song Gao
2023-06-20 9:37 ` [PATCH v1 21/46] target/loongarch: Implement xvsigncov Song Gao
2023-06-20 9:37 ` [PATCH v1 22/46] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz Song Gao
2023-06-20 9:37 ` [PATCH v1 23/46] target/loognarch: Implement xvldi Song Gao
2023-06-20 9:37 ` [PATCH v1 24/46] target/loongarch: Implement LASX logic instructions Song Gao
2023-06-20 9:37 ` [PATCH v1 25/46] target/loongarch: Implement xvsll xvsrl xvsra xvrotr Song Gao
2023-06-20 9:37 ` [PATCH v1 26/46] target/loongarch: Implement xvsllwil xvextl Song Gao
2023-06-20 9:37 ` [PATCH v1 27/46] target/loongarch: Implement xvsrlr xvsrar Song Gao
2023-06-20 9:37 ` [PATCH v1 28/46] target/loongarch: Implement xvsrln xvsran Song Gao
2023-06-20 9:37 ` [PATCH v1 29/46] target/loongarch: Implement xvsrlrn xvsrarn Song Gao
2023-06-20 9:37 ` [PATCH v1 30/46] target/loongarch: Implement xvssrln xvssran Song Gao
2023-06-20 9:37 ` [PATCH v1 31/46] target/loongarch: Implement xvssrlrn xvssrarn Song Gao
2023-06-20 9:38 ` [PATCH v1 32/46] target/loongarch: Implement xvclo xvclz Song Gao
2023-06-20 9:38 ` [PATCH v1 33/46] target/loongarch: Implement xvpcnt Song Gao
2023-06-20 9:38 ` [PATCH v1 34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev Song Gao
2023-06-20 9:38 ` [PATCH v1 35/46] target/loongarch: Implement xvfrstp Song Gao
2023-06-20 9:38 ` [PATCH v1 36/46] target/loongarch: Implement LASX fpu arith instructions Song Gao
2023-06-20 9:38 ` [PATCH v1 37/46] target/loongarch: Implement LASX fpu fcvt instructions Song Gao
2023-06-20 9:38 ` [PATCH v1 38/46] target/loongarch: Implement xvseq xvsle xvslt Song Gao
2023-06-20 9:38 ` [PATCH v1 39/46] target/loongarch: Implement xvfcmp Song Gao
2023-06-20 9:38 ` [PATCH v1 40/46] target/loongarch: Implement xvbitsel xvset Song Gao
2023-06-20 9:38 ` [PATCH v1 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr Song Gao
2023-06-20 9:38 ` [PATCH v1 42/46] target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v Song Gao
2023-06-20 9:38 ` [PATCH v1 43/46] target/loongarch: Implement xvpack xvpick xvilv{l/h} Song Gao
2023-06-20 9:38 ` [PATCH v1 44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins Song Gao
2023-06-20 9:38 ` [PATCH v1 45/46] target/loongarch: Implement xvld xvst Song Gao
2023-06-20 9:38 ` [PATCH v1 46/46] target/loongarch: CPUCFG support LASX Song Gao
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