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Tue, 20 Jun 2023 05:25:22 -0700 (PDT) Message-ID: <47d12e8b-493a-e58c-54a1-47bd919c7e20@linaro.org> Date: Tue, 20 Jun 2023 14:25:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v1 04/46] target/loongarch: Implement xvadd/xvsub Content-Language: en-US To: Song Gao , qemu-devel@nongnu.org References: <20230620093814.123650-1-gaosong@loongson.cn> <20230620093814.123650-5-gaosong@loongson.cn> From: Richard Henderson In-Reply-To: <20230620093814.123650-5-gaosong@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/20/23 11:37, Song Gao wrote: > +static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop, > + void (*func)(unsigned, uint32_t, uint32_t, > + uint32_t, uint32_t, uint32_t)) > +{ > + uint32_t xd_ofs, xj_ofs, xk_ofs; > + > + CHECK_ASXE; > + > + xd_ofs = vec_full_offset(a->xd); > + xj_ofs = vec_full_offset(a->xj); > + xk_ofs = vec_full_offset(a->xk); > + > + func(mop, xd_ofs, xj_ofs, xk_ofs, 32, ctx->vl / 8); > + return true; > +} Comparing gvec_xxx vs gvec_vvv for LSX, > func(mop, vd_ofs, vj_ofs, vk_ofs, 16, ctx->vl/8); gvec_vvv will write 16 bytes of output, followed by 16 bytes of zero to satisfy vl / 8. I presume this is the intended behaviour of mixing LSX with LASX, that the high 128-bits that are not considered by the LSX instruction are zeroed on write? Which means that your macros from patch 1, > +#if HOST_BIG_ENDIAN ... > +#define XB(x) XB[31 - (x)] > +#define XH(x) XH[15 - (x)] are incorrect. We need big-endian within the Int128, but little-endian ordering of the two Int128. This can be done with #define XB(x) XB[(x) ^ 15] #define XH(x) XH[(x) ^ 7] etc. It would be nice to share more code with trans_lsx.c, if possible. r~