* [PATCH] target/i386: fix CPUID check for LFENCE and SFENCE
@ 2024-10-22 5:59 Paolo Bonzini
2024-10-22 14:38 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Paolo Bonzini @ 2024-10-22 5:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Guenter Roeck, qemu-stable
LFENCE and SFENCE were introduced with the original SSE instruction set;
marking them incorrectly as cpuid(SSE2) causes failures for CPU models
that lack SSE2, for example pentium3.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 1f193716468..48bf730cd3e 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -345,9 +345,9 @@ static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
[1] = X86_OP_ENTRYw(RDxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3),
[2] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3 zextT0),
[3] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3 zextT0),
- [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE2) p_00),
+ [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE) p_00),
[6] = X86_OP_ENTRY0(MFENCE, cpuid(SSE2) p_00),
- [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE2) p_00),
+ [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE) p_00),
};
static const X86OpEntry group15_mem[8] = {
--
2.46.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/i386: fix CPUID check for LFENCE and SFENCE
2024-10-22 5:59 [PATCH] target/i386: fix CPUID check for LFENCE and SFENCE Paolo Bonzini
@ 2024-10-22 14:38 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2024-10-22 14:38 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: Guenter Roeck, qemu-stable
On 10/21/24 22:59, Paolo Bonzini wrote:
> LFENCE and SFENCE were introduced with the original SSE instruction set;
> marking them incorrectly as cpuid(SSE2) causes failures for CPU models
> that lack SSE2, for example pentium3.
>
> Reported-by: Guenter Roeck<linux@roeck-us.net>
> Tested-by: Guenter Roeck<linux@roeck-us.net>
> Cc:qemu-stable@nongnu.org
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
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