Index: hw/fdc.c =================================================================== --- hw/fdc.c (revision 4215) +++ hw/fdc.c (working copy) @@ -66,10 +66,6 @@ FDRIVE_DRV_NONE = 0x03, /* No drive connected */ } fdrive_type_t; -typedef enum fdrive_flags_t { - FDRIVE_MOTOR_ON = 0x01, /* motor on/off */ -} fdrive_flags_t; - typedef enum fdisk_flags_t { FDISK_DBL_SIDES = 0x01, } fdisk_flags_t; @@ -78,7 +74,6 @@ BlockDriverState *bs; /* Drive status */ fdrive_type_t drive; - fdrive_flags_t drflags; uint8_t perpendicular; /* 2.88 MB access mode */ /* Position */ uint8_t head; @@ -100,7 +95,6 @@ /* Drive */ drv->bs = bs; drv->drive = FDRIVE_DRV_NONE; - drv->drflags = 0; drv->perpendicular = 0; /* Disk */ drv->last_sect = 0; @@ -293,24 +287,6 @@ } } -/* Motor control */ -static void fd_start (fdrive_t *drv) -{ - drv->drflags |= FDRIVE_MOTOR_ON; -} - -static void fd_stop (fdrive_t *drv) -{ - drv->drflags &= ~FDRIVE_MOTOR_ON; -} - -/* Re-initialise a drives (motor off, repositioned) */ -static void fd_reset (fdrive_t *drv) -{ - fd_stop(drv); - fd_recalibrate(drv); -} - /********************************************************/ /* Intel 82078 floppy disk controller emulation */ @@ -334,7 +310,6 @@ enum { FD_CTRL_ACTIVE = 0x01, /* XXX: suppress that */ - FD_CTRL_RESET = 0x02, FD_CTRL_SLEEP = 0x04, /* XXX: suppress that */ FD_CTRL_BUSY = 0x08, /* dma transfer in progress */ }; @@ -624,10 +599,6 @@ static void fd_save (QEMUFile *f, fdrive_t *fd) { - uint8_t tmp; - - tmp = fd->drflags; - qemu_put_8s(f, &tmp); qemu_put_8s(f, &fd->head); qemu_put_8s(f, &fd->track); qemu_put_8s(f, &fd->sect); @@ -670,10 +641,6 @@ static int fd_load (QEMUFile *f, fdrive_t *fd) { - uint8_t tmp; - - qemu_get_8s(f, &tmp); - fd->drflags = tmp; qemu_get_8s(f, &fd->head); qemu_get_8s(f, &fd->track); qemu_get_8s(f, &fd->sect); @@ -779,7 +746,7 @@ if (!fdctrl->drives[1].bs) fdctrl->sra |= FD_SRA_nDRV2; fdctrl->cur_drv = 0; - fdctrl->dor = 0; + fdctrl->dor = FD_DOR_nRESET; fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; /* FIFO state */ fdctrl->data_pos = 0; @@ -787,7 +754,7 @@ fdctrl->data_state = FD_STATE_CMD; fdctrl->data_dir = FD_DIR_WRITE; for (i = 0; i < MAX_FD; i++) - fd_reset(&fdctrl->drives[i]); + fd_recalibrate(&fdctrl->drives[i]); fdctrl_reset_fifo(fdctrl); if (do_irq) { fdctrl->status0 |= FD_SR0_RDYCHG; @@ -833,19 +800,8 @@ /* Digital output register : 0x02 */ static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl) { - uint32_t retval = 0; + uint32_t retval = fdctrl->dor; - /* Drive motors state indicators */ - if (drv0(fdctrl)->drflags & FDRIVE_MOTOR_ON) - retval |= FD_DOR_MOTEN0; - if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON) - retval |= FD_DOR_MOTEN1; - /* DMA enable */ - if (fdctrl->dor & FD_DOR_DMAEN) - retval |= FD_DOR_DMAEN; - /* Reset indicator */ - if (!(fdctrl->state & FD_CTRL_RESET)) - retval |= FD_DOR_nRESET; /* Selected drive */ retval |= fdctrl->cur_drv; FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); @@ -855,13 +811,6 @@ static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value) { - /* Reset mode */ - if (fdctrl->state & FD_CTRL_RESET) { - if (!(value & FD_DOR_nRESET)) { - FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); - return; - } - } FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); /* Motors */ @@ -880,26 +829,16 @@ else fdctrl->srb &= ~FD_SRB_DR0; - /* Drive motors state indicators */ - if (value & FD_DOR_MOTEN1) - fd_start(drv1(fdctrl)); - else - fd_stop(drv1(fdctrl)); - if (value & FD_DOR_MOTEN0) - fd_start(drv0(fdctrl)); - else - fd_stop(drv0(fdctrl)); /* Reset */ if (!(value & FD_DOR_nRESET)) { - if (!(fdctrl->state & FD_CTRL_RESET)) { + if (fdctrl->dor & FD_DOR_nRESET) { FLOPPY_DPRINTF("controller enter RESET state\n"); - fdctrl->state |= FD_CTRL_RESET; } } else { - if (fdctrl->state & FD_CTRL_RESET) { + if (!(fdctrl->dor & FD_DOR_nRESET)) { FLOPPY_DPRINTF("controller out of RESET state\n"); fdctrl_reset(fdctrl, 1); - fdctrl->state &= ~(FD_CTRL_RESET | FD_CTRL_SLEEP); + fdctrl->state &= ~FD_CTRL_SLEEP; } } /* Selected drive */ @@ -924,7 +863,7 @@ static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value) { /* Reset mode */ - if (fdctrl->state & FD_CTRL_RESET) { + if (!(fdctrl->dor & FD_DOR_nRESET)) { FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); return; } @@ -939,7 +878,8 @@ { uint32_t retval = 0; - fdctrl->state &= ~(FD_CTRL_SLEEP | FD_CTRL_RESET); + fdctrl->dor |= FD_DOR_nRESET; + fdctrl->state &= ~FD_CTRL_SLEEP; if (!(fdctrl->state & FD_CTRL_BUSY)) { /* Data transfer allowed */ retval |= FD_MSR_RQM; @@ -963,16 +903,16 @@ static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value) { /* Reset mode */ - if (fdctrl->state & FD_CTRL_RESET) { + if (!(fdctrl->dor & FD_DOR_nRESET)) { FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); return; } FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); /* Reset: autoclear */ if (value & FD_DSR_SWRESET) { - fdctrl->state |= FD_CTRL_RESET; + fdctrl->dor &= ~FD_DOR_nRESET; fdctrl_reset(fdctrl, 1); - fdctrl->state &= ~FD_CTRL_RESET; + fdctrl->dor |= FD_DOR_nRESET; } if (value & FD_DSR_PWRDOWN) { fdctrl->state |= FD_CTRL_SLEEP; @@ -1610,7 +1550,6 @@ fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK; cur_drv = get_cur_drv(fdctrl); - fd_start(cur_drv); if (fdctrl->fifo[2] <= cur_drv->track) cur_drv->dir = 1; else @@ -1684,7 +1623,6 @@ fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK; cur_drv = get_cur_drv(fdctrl); - fd_start(cur_drv); cur_drv->dir = 0; if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { cur_drv->track = cur_drv->max_track - 1; @@ -1702,7 +1640,6 @@ fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK; cur_drv = get_cur_drv(fdctrl); - fd_start(cur_drv); cur_drv->dir = 1; if (fdctrl->fifo[2] > cur_drv->track) { cur_drv->track = 0; @@ -1766,7 +1703,7 @@ cur_drv = get_cur_drv(fdctrl); /* Reset mode */ - if (fdctrl->state & FD_CTRL_RESET) { + if (!(fdctrl->dor & FD_DOR_nRESET)) { FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); return; }