From: Anthony Liguori <aliguori@us.ibm.com>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: kvm-devel@lists.sourceforge.net,
Marcelo Tosatti <marcelo@kvack.org>,
qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>,
Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] [PATCH 1/5] PCI DMA API (v3)
Date: Thu, 17 Apr 2008 15:05:59 -0500 [thread overview]
Message-ID: <4807ADA7.7000500@us.ibm.com> (raw)
In-Reply-To: <f43fc5580804171227q4ff3fd2cv9e94076597253e9f@mail.gmail.com>
Blue Swirl wrote:
>
> I fixed the bug, now pcnet works. Performance is improved by a few
> percent. The problem was that the vector was not freed. Maybe dynamic
> allocation is a bit fragile. In this case, the length of the vector is
> known, so it could be allocated once at init time. But would this
> work?
>
For you, yes, but not for me. virtio scatter/gather lists can be very
long. The API tries not to make assumptions about who's allocating what
so you should be able to get away without a dynamic allocation if you
were sufficiently motivated.
> The next step would be to add a vector version for packet receive. For
> ESP/SCSI, in addition to bdrv_readv/writev, AIO versions would need to
> be added. Last year I made a patch (attached) that made SLIRP use my
> version of IOVector, I could update it to this model.
>
Yes, the vector version of packet receive is tough. I'll take a look at
your patch. Basically, you need to associate a set of RX vectors with
each VLANClientState and then when it comes time to deliver a packet to
the VLAN, before calling fd_read, see if there is an RX vector available
for the client.
In the case of tap, I want to optimize further and do the initial
readv() to one of the clients RX buffers and then copy that RX buffer to
the rest of the clients if necessary.
Regards,
Anthony Liguori
>>> IMHO the read/write functions should be a property of the bus so that
>>> they are hidden from the device, for pcnet it does not matter as we
>>> have to do the swapping anyway.
>>>
>>>
>>>
>> For an IOMMU that has a per-device mapping, the read/write functions have
>> to operate on a per-device basis.
>>
>
> No, I meant that there could be a bus layer that did the memory access
> and provided a specialized version of iovector_new without the
> handlers. But I think we can live with this, if things get too ugly we
> can add the layering later.
>
next prev parent reply other threads:[~2008-04-17 20:06 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-04-15 22:11 [Qemu-devel] [PATCH 1/5] PCI DMA API (v3) Anthony Liguori
2008-04-15 22:11 ` [Qemu-devel] [PATCH 2/5] virtio for QEMU (v3) Anthony Liguori
2008-04-15 22:11 ` [Qemu-devel] [PATCH 3/5] virtio network driver (v3) Anthony Liguori
2008-04-15 22:11 ` [Qemu-devel] [PATCH 4/5] virtio block " Anthony Liguori
2008-04-15 22:11 ` [Qemu-devel] [PATCH 5/5] virtio balloon " Anthony Liguori
2008-04-16 19:51 ` [Qemu-devel] [PATCH 1/5] PCI DMA API (v3) Blue Swirl
2008-04-16 19:54 ` Anthony Liguori
2008-04-17 19:27 ` Blue Swirl
2008-04-17 20:05 ` Anthony Liguori [this message]
2008-04-19 19:40 ` Blue Swirl
2008-04-19 20:02 ` [kvm-devel] " Anthony Liguori
2008-04-20 6:42 ` Blue Swirl
2008-04-20 19:29 ` Anthony Liguori
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