From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K2nbe-0006gk-7G for qemu-devel@nongnu.org; Sun, 01 Jun 2008 09:28:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K2nbd-0006gI-Lv for qemu-devel@nongnu.org; Sun, 01 Jun 2008 09:28:17 -0400 Received: from [199.232.76.173] (port=43040 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K2nbd-0006g1-Ds for qemu-devel@nongnu.org; Sun, 01 Jun 2008 09:28:17 -0400 Received: from moutng.kundenserver.de ([212.227.126.187]:59631) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1K2nbd-0003bN-1U for qemu-devel@nongnu.org; Sun, 01 Jun 2008 09:28:17 -0400 Message-ID: <4842A3EC.9070309@mail.berlios.de> Date: Sun, 01 Jun 2008 15:28:12 +0200 From: Stefan Weil MIME-Version: 1.0 Subject: Re: [Qemu-devel] [4496][Bug] Switch most MIPS logical and arithmetic instructions to TCG. References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Thiemo Seufer Since Qemu r4496, r4497, MIPS Malta no longer boots in big endian mode (little endian still works). The Linux kernel hangs in prom_putchar. A comparision of qemu.log shows a regression for at least rotr (see extracts of qemu.log for r4495 and r4497). There seems to be another regression for the code in prom_putchar. r4497 also changes the initial values of the register HI, LO. I patched these differences in the listings below. Stefan r4495 (register a2 changes correctly): pc=0x80458760 HI=0x033d59d4 LO=0x033d5a24 ds 0090 80458740 0 GPR00: r0 00000000 at 00000008 v0 c0000000 v1 c0000000 GPR04: a0 bbe00000 a1 80480000 a2 00c00000 a3 bbe00048 GPR08: t0 bbe000f0 t1 00000020 t2 000000a0 t3 80490000 GPR12: t4 80480000 t5 80480000 t6 8042fe2e t7 ffffffff GPR16: s0 80480000 s1 8042ffa0 s2 00000000 s3 00000000 GPR20: s4 00000000 s5 00000000 s6 80480000 s7 00000000 GPR24: t8 00000001 t9 00000006 k0 00000000 k1 00000000 GPR28: gp 8042e000 sp 8042ff08 s8 00000000 ra 80458564 CP0 Status 0x10000000 Cause 0x00000400 EPC 0x00000000 Config0 0x80008482 Config1 0x9e190c8b LLAddr 0x804322dc IN: prom_init 0x80458760: ror a2,a2,0x10 ---------------- 0 00000090 OP: ld_i32 T0,current_tc_gprs,$0x18 movi_i32 T1,$0x10 rotr st_i32 T0,current_tc_gprs,$0x18 goto_tb $0x0 save_pc $0x80458764 exit_tb $0xbb7748 ------------------------------------------------ pc=0x80458764 HI=0x033d59d4 LO=0x033d5a24 ds 0090 80458740 0 GPR00: r0 00000000 at 00000008 v0 c0000000 v1 c0000000 GPR04: a0 bbe00000 a1 80480000 a2 000000c0 a3 bbe00048 GPR08: t0 bbe000f0 t1 00000020 t2 000000a0 t3 80490000 GPR12: t4 80480000 t5 80480000 t6 8042fe2e t7 ffffffff GPR16: s0 80480000 s1 8042ffa0 s2 00000000 s3 00000000 r4497 and later (register a2 remains unchanged): pc=0x80458760 HI=0x03a609d4 LO=0x03a60a24 ds 0090 80458740 0 GPR00: r0 00000000 at 00000008 v0 c0000000 v1 c0000000 GPR04: a0 bbe00000 a1 80480000 a2 00c00000 a3 bbe00048 GPR08: t0 bbe000f0 t1 00000020 t2 000000a0 t3 80490000 GPR12: t4 80480000 t5 80480000 t6 8042fe2e t7 ffffffff GPR16: s0 80480000 s1 8042ffa0 s2 00000000 s3 00000000 GPR20: s4 00000000 s5 00000000 s6 80480000 s7 00000000 GPR24: t8 00000001 t9 00000006 k0 00000000 k1 00000000 GPR28: gp 8042e000 sp 8042ff08 s8 00000000 ra 80458564 CP0 Status 0x10000000 Cause 0x00000400 EPC 0x00000000 Config0 0x80008482 Config1 0x9e190c8b LLAddr 0x804322dc IN: prom_init 0x80458760: ror a2,a2,0x10 ---------------- 0 00000090 OP: ld_i32 T0,current_tc_gprs,$0x18 mov_i32 tmp0,T0 movi_i32 tmp1,$0x20 sub_i32 tmp1,tmp1,$0x10 shl_i32 tmp1,tmp0,tmp1 shr_i32 tmp0,tmp0,$0x10 or_i32 tmp0,tmp0,tmp1 mov_i32 tmp0,T0 st_i32 T0,current_tc_gprs,$0x18 goto_tb $0x0 save_pc $0x80458764 exit_tb $0xbbefe8 ------------------------------------------------ pc=0x80458764 HI=0x03a609d4 LO=0x03a60a24 ds 0090 80458740 0 GPR00: r0 00000000 at 00000008 v0 c0000000 v1 c0000000 GPR04: a0 bbe00000 a1 80480000 a2 00c00000 a3 bbe00048 GPR08: t0 bbe000f0 t1 00000020 t2 000000a0 t3 80490000 GPR12: t4 80480000 t5 80480000 t6 8042fe2e t7 ffffffff GPR16: s0 80480000 s1 8042ffa0 s2 00000000 s3 00000000 GPR20: s4 00000000 s5 00000000 s6 80480000 s7 00000000 Thiemo Seufer schrieb: > Revision: 4496 > http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4496 > Author: ths > Date: 2008-05-18 22:50:49 +0000 (Sun, 18 May 2008) > > Log Message: > ----------- > Switch most MIPS logical and arithmetic instructions to TCG. > > Modified Paths: > -------------- > trunk/target-mips/exec.h > trunk/target-mips/op.c > trunk/target-mips/op_helper.c > trunk/target-mips/translate.c > trunk/tcg/tcg-op.h