From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K3yAD-0003xO-Ks for qemu-devel@nongnu.org; Wed, 04 Jun 2008 14:56:49 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K3yAC-0003wD-18 for qemu-devel@nongnu.org; Wed, 04 Jun 2008 14:56:48 -0400 Received: from [199.232.76.173] (port=54258 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K3yAB-0003w1-QT for qemu-devel@nongnu.org; Wed, 04 Jun 2008 14:56:47 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:58689) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1K3yAB-0007Tn-Eo for qemu-devel@nongnu.org; Wed, 04 Jun 2008 14:56:47 -0400 Received: from smtp08.web.de (fmsmtp08.dlan.cinetic.de [172.20.5.216]) by fmmailgate02.web.de (Postfix) with ESMTP id 975A8DFFD819 for ; Wed, 4 Jun 2008 20:56:46 +0200 (CEST) Received: from [88.65.37.28] (helo=[139.25.109.167]) by smtp08.web.de with asmtp (TLSv1:AES256-SHA:256) (WEB.DE 4.109 #226) id 1K3yA9-0000ZB-00 for qemu-devel@nongnu.org; Wed, 04 Jun 2008 20:56:46 +0200 Resent-To: qemu-devel@nongnu.org Resent-Message-Id: <4846E56D.4080104@web.de> Message-ID: <4846E4A6.9070707@web.de> Date: Wed, 04 Jun 2008 20:53:26 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <4846E354.805@web.de> In-Reply-To: <4846E354.805@web.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Sender: jan.kiszka@web.de Subject: [Qemu-devel] [PATCH 1/3] Introduce SSTEP_INTERNAL Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Introducing SSTEP_INTERNAL, this patch allows to reuse the (host-injected) single-step infrastructure to let the emulator generate and execute TBs that only include one instruction. Signed-off-by: Jan Kiszka --- cpu-all.h | 7 ++++--- cpu-exec.c | 4 +++- exec.c | 2 ++ gdbstub.c | 4 ++-- target-arm/translate.c | 2 +- target-cris/translate.c | 2 +- target-i386/translate.c | 2 +- target-m68k/translate.c | 4 ++-- target-mips/translate.c | 2 +- target-ppc/translate.c | 2 +- target-sh4/translate.c | 6 +++--- vl.c | 7 ++++--- 12 files changed, 25 insertions(+), 19 deletions(-) Index: b/cpu-all.h =================================================================== --- a/cpu-all.h +++ b/cpu-all.h @@ -804,9 +804,10 @@ int cpu_breakpoint_insert(CPUState *env, int cpu_breakpoint_remove(CPUState *env, target_ulong pc); void cpu_breakpoint_remove_all(CPUState *env); -#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ -#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ -#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ +#define SSTEP_DEBUG 0x1 /* Enable simulated HW single stepping */ +#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ +#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ +#define SSTEP_INTERNAL 0x8 /* QEMU internal, do not generate breakpoint */ void cpu_single_step(CPUState *env, int enabled); void cpu_reset(CPUState *s); Index: b/cpu-exec.c =================================================================== --- a/cpu-exec.c +++ b/cpu-exec.c @@ -369,7 +369,8 @@ int cpu_exec(CPUState *env1) for(;;) { interrupt_request = env->interrupt_request; if (__builtin_expect(interrupt_request, 0) && - likely(!(env->singlestep_enabled & SSTEP_NOIRQ))) { + likely(!(env->singlestep_enabled & + (SSTEP_NOIRQ | SSTEP_INTERNAL)))) { if (interrupt_request & CPU_INTERRUPT_DEBUG) { env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; env->exception_index = EXCP_DEBUG; @@ -609,6 +610,7 @@ int cpu_exec(CPUState *env1) #endif next_tb = tcg_qemu_tb_exec(tc_ptr); env->current_tb = NULL; + env->singlestep_enabled &= ~SSTEP_INTERNAL; /* reset soft MMU for next block (it can currently only be set by a memory fault) */ #if defined(USE_KQEMU) Index: b/exec.c =================================================================== --- a/exec.c +++ b/exec.c @@ -1292,6 +1292,8 @@ int cpu_breakpoint_remove(CPUState *env, void cpu_single_step(CPUState *env, int enabled) { #if defined(TARGET_HAS_ICE) + enabled &= SSTEP_DEBUG | SSTEP_NOIRQ | SSTEP_NOTIMER; + enabled |= env->singlestep_enabled & SSTEP_INTERNAL; if (env->singlestep_enabled != enabled) { env->singlestep_enabled = enabled; /* must flush all the translated code to avoid inconsistancies */ Index: b/target-arm/translate.c =================================================================== --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8666,7 +8666,7 @@ static inline int gen_intermediate_code_ /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ - if (__builtin_expect(env->singlestep_enabled, 0)) { + if (__builtin_expect(env->singlestep_enabled & SSTEP_DEBUG, 0)) { /* Make sure the pc is updated, and raise a debug exception. */ if (dc->condjmp) { gen_set_condexec(dc); Index: b/target-cris/translate.c =================================================================== --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3067,7 +3067,7 @@ gen_intermediate_code_internal(CPUState cris_evaluate_flags (dc); done: - if (__builtin_expect(env->singlestep_enabled, 0)) { + if (__builtin_expect(env->singlestep_enabled & SSTEP_DEBUG, 0)) { t_gen_raise_exception(EXCP_DEBUG); } else { switch(dc->is_jmp) { Index: b/target-i386/translate.c =================================================================== --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2618,7 +2618,7 @@ static void gen_eob(DisasContext *s) if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { tcg_gen_helper_0_0(helper_reset_inhibit_irq); } - if (s->singlestep_enabled) { + if (s->singlestep_enabled & SSTEP_DEBUG) { tcg_gen_helper_0_0(helper_debug); } else if (s->tf) { tcg_gen_helper_0_0(helper_single_step); Index: b/target-m68k/translate.c =================================================================== --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -871,7 +871,7 @@ static void gen_jmp_tb(DisasContext *s, TranslationBlock *tb; tb = s->tb; - if (__builtin_expect (s->singlestep_enabled, 0)) { + if (__builtin_expect (s->singlestep_enabled & SSTEP_DEBUG, 0)) { gen_exception(s, dest, EXCP_DEBUG); } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { @@ -2974,7 +2974,7 @@ gen_intermediate_code_internal(CPUState !env->singlestep_enabled && (pc_offset) < (TARGET_PAGE_SIZE - 32)); - if (__builtin_expect(env->singlestep_enabled, 0)) { + if (__builtin_expect(env->singlestep_enabled & SSTEP_DEBUG, 0)) { /* Make sure the pc is updated, and raise a debug exception. */ if (!dc->is_jmp) { gen_flush_cc_op(dc); Index: b/target-mips/translate.c =================================================================== --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -7259,7 +7259,7 @@ gen_intermediate_code_internal (CPUState break; #endif } - if (env->singlestep_enabled) { + if (env->singlestep_enabled & SSTEP_DEBUG) { save_cpu_state(&ctx, ctx.bstate == BS_NONE); gen_op_debug(); } else { Index: b/target-ppc/translate.c =================================================================== --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6319,7 +6319,7 @@ static always_inline int gen_intermediat if (ctx.exception == POWERPC_EXCP_NONE) { gen_goto_tb(&ctx, 0, ctx.nip); } else if (ctx.exception != POWERPC_EXCP_BRANCH) { - if (unlikely(env->singlestep_enabled)) { + if (unlikely(env->singlestep_enabled & SSTEP_DEBUG)) { gen_update_nip(&ctx, ctx.nip); gen_op_debug(); } Index: b/target-sh4/translate.c =================================================================== --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -161,7 +161,7 @@ static void gen_goto_tb(DisasContext * c tcg_gen_exit_tb((long) tb + n); } else { gen_op_movl_imm_PC(dest); - if (ctx->singlestep_enabled) + if (ctx->singlestep_enabled & SSTEP_DEBUG) gen_op_debug(); tcg_gen_exit_tb(0); } @@ -173,7 +173,7 @@ static void gen_jump(DisasContext * ctx) /* Target is not statically known, it comes necessarily from a delayed jump as immediate jump are conditinal jumps */ gen_op_movl_delayed_pc_PC(); - if (ctx->singlestep_enabled) + if (ctx->singlestep_enabled & SSTEP_DEBUG) gen_op_debug(); tcg_gen_exit_tb(0); } else { @@ -1251,7 +1251,7 @@ gen_intermediate_code_internal(CPUState break; #endif } - if (env->singlestep_enabled) { + if (env->singlestep_enabled & SSTEP_DEBUG) { gen_op_debug(); } else { switch (ctx.bstate) { Index: b/vl.c =================================================================== --- a/vl.c +++ b/vl.c @@ -7032,9 +7032,10 @@ void main_loop_wait(int timeout) qemu_aio_poll(); if (vm_running) { - if (likely(!(cur_cpu->singlestep_enabled & SSTEP_NOTIMER))) - qemu_run_timers(&active_timers[QEMU_TIMER_VIRTUAL], - qemu_get_clock(vm_clock)); + if (likely(!(cur_cpu->singlestep_enabled & + (SSTEP_NOTIMER | SSTEP_INTERNAL)))) + qemu_run_timers(&active_timers[QEMU_TIMER_VIRTUAL], + qemu_get_clock(vm_clock)); /* run dma transfers, if any */ DMA_run(); } Index: b/gdbstub.c =================================================================== --- a/gdbstub.c +++ b/gdbstub.c @@ -77,7 +77,7 @@ typedef struct GDBState { /* By default use no IRQs and no timers while single stepping so as to * make single stepping like an ICE HW step. */ -static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER; +static int sstep_flags = SSTEP_DEBUG | SSTEP_NOIRQ | SSTEP_NOTIMER; #ifdef CONFIG_USER_ONLY /* XXX: This is not thread safe. Do we care? */ @@ -1144,7 +1144,7 @@ static int gdb_handle_packet(GDBState *s if (!strcmp(p,"qemu.sstepbits")) { /* Query Breakpoint bit definitions */ sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x", - SSTEP_ENABLE, + SSTEP_DEBUG, SSTEP_NOIRQ, SSTEP_NOTIMER); put_packet(s, buf);