From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KB5cd-00064V-SA for qemu-devel@nongnu.org; Tue, 24 Jun 2008 06:19:36 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KB5cZ-00063X-5G for qemu-devel@nongnu.org; Tue, 24 Jun 2008 06:19:34 -0400 Received: from [199.232.76.173] (port=56340 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KB5cX-00063A-I3 for qemu-devel@nongnu.org; Tue, 24 Jun 2008 06:19:30 -0400 Received: from gecko.sbs.de ([194.138.37.40]:17072) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KB5cW-0006Xa-P3 for qemu-devel@nongnu.org; Tue, 24 Jun 2008 06:19:29 -0400 Received: from mail2.sbs.de (localhost [127.0.0.1]) by gecko.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m5OAJI0N011236 for ; Tue, 24 Jun 2008 12:19:18 +0200 Received: from [139.25.109.167] (mchn012c.mchp.siemens.de [139.25.109.167] (may be forged)) by mail2.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m5OAJISR020133 for ; Tue, 24 Jun 2008 12:19:18 +0200 Message-ID: <4860CA25.7050508@siemens.com> Date: Tue, 24 Jun 2008 12:19:17 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <485FBE12.5080100@siemens.com> <4860B958.1010306@suse.de> In-Reply-To: <4860B958.1010306@suse.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 1/2] Log reset events - v2 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Kevin Wolf wrote: > Jan Kiszka schrieb: >> Index: b/target-i386/helper.c >> =================================================================== >> --- a/target-i386/helper.c >> +++ b/target-i386/helper.c >> @@ -383,6 +383,11 @@ void cpu_reset(CPUX86State *env) >> >> memset(env, 0, offsetof(CPUX86State, breakpoints)); >> >> + if (loglevel & CPU_LOG_RESET) { >> + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); >> + cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | >> X86_DUMP_CCOP); >> + } >> + >> tlb_flush(env, 1); >> >> env->old_exception = -1; > > I'd say you want to have the memset after the CPU dump, otherwise the > dump is quite boring. ;-) Did you change that by intention? Your last > patch still had the memset after the dump. Good point, probably merge breakage. Moreover my patch was ignoring archs != x86. Better version below. ----------- Original idea&code by Kevin Wolf, now split-up in two patches and added more archs. This patch introduces a flag to log CPU resets. Useful for tracing unexpected resets (such as those triggered by x86 triple faults). Signed-off-by: Jan Kiszka Acked-by: Kevin Wolf --- cpu-all.h | 1 + exec.c | 2 ++ target-arm/helper.c | 6 ++++++ target-cris/translate.c | 5 +++++ target-i386/helper.c | 5 +++++ target-m68k/helper.c | 5 +++++ target-mips/translate.c | 5 +++++ target-ppc/helper.c | 5 +++++ target-sh4/translate.c | 5 +++++ target-sparc/helper.c | 5 +++++ 10 files changed, 44 insertions(+) Index: b/exec.c =================================================================== --- a/exec.c +++ b/exec.c @@ -1417,6 +1417,8 @@ CPULogItem cpu_log_items[] = { #ifdef TARGET_I386 { CPU_LOG_PCALL, "pcall", "show protected mode far calls/returns/exceptions" }, + { CPU_LOG_RESET, "cpu_reset", + "show CPU state before CPU resets" }, #endif #ifdef DEBUG_IOPORT { CPU_LOG_IOPORT, "ioport", Index: b/target-i386/helper.c =================================================================== --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -381,6 +381,11 @@ void cpu_reset(CPUX86State *env) { int i; + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); + } + memset(env, 0, offsetof(CPUX86State, breakpoints)); tlb_flush(env, 1); Index: b/cpu-all.h =================================================================== --- a/cpu-all.h +++ b/cpu-all.h @@ -825,6 +825,7 @@ target_phys_addr_t cpu_get_phys_page_deb #define CPU_LOG_PCALL (1 << 6) #define CPU_LOG_IOPORT (1 << 7) #define CPU_LOG_TB_CPU (1 << 8) +#define CPU_LOG_RESET (1 << 9) /* define log items */ typedef struct CPULogItem { Index: b/target-arm/helper.c =================================================================== --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -153,6 +153,12 @@ static void cpu_reset_model_id(CPUARMSta void cpu_reset(CPUARMState *env) { uint32_t id; + + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, 0); + } + id = env->cp15.c0_cpuid; memset(env, 0, offsetof(CPUARMState, breakpoints)); if (id) Index: b/target-cris/translate.c =================================================================== --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3360,6 +3360,11 @@ CPUCRISState *cpu_cris_init (const char void cpu_reset (CPUCRISState *env) { + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, 0); + } + memset(env, 0, offsetof(CPUCRISState, breakpoints)); tlb_flush(env, 1); Index: b/target-m68k/helper.c =================================================================== --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -110,6 +110,11 @@ static int cpu_m68k_set_model(CPUM68KSta void cpu_reset(CPUM68KState *env) { + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, 0); + } + memset(env, 0, offsetof(CPUM68KState, breakpoints)); #if !defined (CONFIG_USER_ONLY) env->sr = 0x2700; Index: b/target-mips/translate.c =================================================================== --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -7989,6 +7989,11 @@ CPUMIPSState *cpu_mips_init (const char void cpu_reset (CPUMIPSState *env) { + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, 0); + } + memset(env, 0, offsetof(CPUMIPSState, breakpoints)); tlb_flush(env, 1); Index: b/target-ppc/helper.c =================================================================== --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2931,6 +2931,11 @@ void cpu_ppc_reset (void *opaque) CPUPPCState *env; target_ulong msr; + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, 0); + } + env = opaque; msr = (target_ulong)0; if (0) { Index: b/target-sh4/translate.c =================================================================== --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -118,6 +118,11 @@ void cpu_dump_state(CPUState * env, FILE void cpu_sh4_reset(CPUSH4State * env) { + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, 0); + } + #if defined(CONFIG_USER_ONLY) env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */ #else Index: b/target-sparc/helper.c =================================================================== --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -881,6 +881,11 @@ void memcpy32(target_ulong *dst, const t void cpu_reset(CPUSPARCState *env) { + if (loglevel & CPU_LOG_RESET) { + fprintf(logfile, "CPU Reset (CPU %d)\n", env->cpu_index); + cpu_dump_state(env, logfile, fprintf, 0); + } + tlb_flush(env, 1); env->cwp = 0; env->wim = 1;