From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KDibs-0002DF-5C for qemu-devel@nongnu.org; Tue, 01 Jul 2008 12:21:40 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KDibq-0002D3-KS for qemu-devel@nongnu.org; Tue, 01 Jul 2008 12:21:38 -0400 Received: from [199.232.76.173] (port=38496 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KDibq-0002D0-DH for qemu-devel@nongnu.org; Tue, 01 Jul 2008 12:21:38 -0400 Received: from lizzard.sbs.de ([194.138.37.39]:19295) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KDibq-0002vT-2o for qemu-devel@nongnu.org; Tue, 01 Jul 2008 12:21:38 -0400 Received: from mail2.sbs.de (localhost [127.0.0.1]) by lizzard.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m61GLXRR007885 for ; Tue, 1 Jul 2008 18:21:34 +0200 Received: from [139.25.109.167] (mchn012c.mchp.siemens.de [139.25.109.167] (may be forged)) by mail2.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m61GLXFK027568 for ; Tue, 1 Jul 2008 18:21:33 +0200 Message-ID: <486A598C.2000005@siemens.com> Date: Tue, 01 Jul 2008 18:21:32 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <4858F482.9050903@siemens.com> In-Reply-To: <4858F482.9050903@siemens.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [RESEND][PATCH] save/restore interrupt_request across snapshots Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org [ Rebased to latest SVN ] Save interrupt_request state along with the cpu snapshot and restore it properly. This also solves the bug that pending interrupts before invocation of qemu_loadvm_state can tunnel into the resumed guest, causing invalid IRQs there. Implementation covers ARM, CRIS, x86, and SPARC, ie. those archs that support snapshotting so far. Signed-off-by: Jan Kiszka --- target-arm/cpu.h | 2 +- target-arm/machine.c | 10 +++++++++- target-cris/cpu.h | 2 +- target-cris/machine.c | 11 +++++++++++ target-i386/cpu.h | 2 +- target-i386/machine.c | 9 ++++++++- target-sparc/cpu.h | 2 +- target-sparc/machine.c | 9 ++++++++- 8 files changed, 40 insertions(+), 7 deletions(-) Index: b/target-i386/machine.c =================================================================== --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -135,6 +135,8 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be16s(f, &env->intercept_dr_write); qemu_put_be32s(f, &env->intercept_exceptions); qemu_put_8s(f, &env->v_tpr); + + qemu_put_be32s(f, (uint32_t *)&env->interrupt_request); } #ifdef USE_X86LDOUBLE @@ -169,7 +171,7 @@ int cpu_load(QEMUFile *f, void *opaque, uint16_t fpus, fpuc, fptag, fpregs_format; int32_t a20_mask; - if (version_id != 3 && version_id != 4 && version_id != 5) + if (version_id < 3 || version_id > CPU_SAVE_VERSION) return -EINVAL; for(i = 0; i < CPU_NB_REGS; i++) qemu_get_betls(f, &env->regs[i]); @@ -292,6 +294,11 @@ int cpu_load(QEMUFile *f, void *opaque, qemu_get_be32s(f, &env->intercept_exceptions); qemu_get_8s(f, &env->v_tpr); } + if (version_id >= 6) { + qemu_get_be32s(f, (uint32_t *)&env->interrupt_request); + } else { + env->interrupt_request = 0; + } /* XXX: ensure compatiblity for halted bit ? */ /* XXX: compute redundant hflags bits */ env->hflags = hflags; Index: b/target-arm/cpu.h =================================================================== --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -397,7 +397,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 1 +#define CPU_SAVE_VERSION 2 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel Index: b/target-arm/machine.c =================================================================== --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -113,6 +113,8 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->v7m.current_sp); qemu_put_be32(f, env->v7m.exception); } + + qemu_put_be32s(f, (uint32_t *)&env->interrupt_request); } int cpu_load(QEMUFile *f, void *opaque, int version_id) @@ -120,7 +122,7 @@ int cpu_load(QEMUFile *f, void *opaque, CPUARMState *env = (CPUARMState *)opaque; int i; - if (version_id != CPU_SAVE_VERSION) + if (version_id < 1 || version_id > CPU_SAVE_VERSION) return -EINVAL; for (i = 0; i < 16; i++) { @@ -209,6 +211,12 @@ int cpu_load(QEMUFile *f, void *opaque, env->v7m.exception = qemu_get_be32(f); } + if (version_id >= 2) { + qemu_get_be32s(f, (uint32_t *)&env->interrupt_request); + } else { + env->interrupt_request = 0; + } + return 0; } Index: b/target-cris/machine.c =================================================================== --- a/target-cris/machine.c +++ b/target-cris/machine.c @@ -47,6 +47,8 @@ void cpu_save(QEMUFile *f, void *opaque) } } } + + qemu_put_be32s(f, (uint32_t *)&env->interrupt_request); } int cpu_load(QEMUFile *f, void *opaque, int version_id) @@ -56,6 +58,9 @@ int cpu_load(QEMUFile *f, void *opaque, int s; int mmu; + if (version_id < 1 || version_id > CPU_SAVE_VERSION) + return -EINVAL; + for (i = 0; i < 16; i++) env->regs[i] = qemu_get_be32(f); for (i = 0; i < 16; i++) @@ -91,5 +96,11 @@ int cpu_load(QEMUFile *f, void *opaque, } } + if (version_id >= 2) { + qemu_get_be32s(f, (uint32_t *)&env->interrupt_request); + } else { + env->interrupt_request = 0; + } + return 0; } Index: b/target-sparc/machine.c =================================================================== --- a/target-sparc/machine.c +++ b/target-sparc/machine.c @@ -58,6 +58,8 @@ void cpu_save(QEMUFile *f, void *opaque) for(i = 0; i < 16; i++) qemu_put_be32s(f, &env->mmuregs[i]); #endif + + qemu_put_be32s(f, (uint32_t *)&env->interrupt_request); } int cpu_load(QEMUFile *f, void *opaque, int version_id) @@ -66,7 +68,7 @@ int cpu_load(QEMUFile *f, void *opaque, int i; uint32_t tmp; - if (version_id != 4) + if (version_id < 4 || version_id > CPU_SAVE_VERSION) return -EINVAL; for(i = 0; i < 8; i++) qemu_get_betls(f, &env->gregs[i]); @@ -99,6 +101,11 @@ int cpu_load(QEMUFile *f, void *opaque, for(i = 0; i < 16; i++) qemu_get_be32s(f, &env->mmuregs[i]); #endif + if (version_id >= 5) { + qemu_get_be32s(f, (uint32_t *)&env->interrupt_request); + } else { + env->interrupt_request = 0; + } tlb_flush(env, 1); return 0; } Index: b/target-cris/cpu.h =================================================================== --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -210,7 +210,7 @@ enum { #define cpu_gen_code cpu_cris_gen_code #define cpu_signal_handler cpu_cris_signal_handler -#define CPU_SAVE_VERSION 1 +#define CPU_SAVE_VERSION 2 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel Index: b/target-i386/cpu.h =================================================================== --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -726,7 +726,7 @@ static inline int cpu_get_time_fast(void #define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list -#define CPU_SAVE_VERSION 5 +#define CPU_SAVE_VERSION 6 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel Index: b/target-sparc/cpu.h =================================================================== --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -388,7 +388,7 @@ void cpu_check_irqs(CPUSPARCState *env); #define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list -#define CPU_SAVE_VERSION 4 +#define CPU_SAVE_VERSION 5 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _user