From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KEtNj-0003U7-D8 for qemu-devel@nongnu.org; Fri, 04 Jul 2008 18:03:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KEtNi-0003Ta-EZ for qemu-devel@nongnu.org; Fri, 04 Jul 2008 18:03:55 -0400 Received: from [199.232.76.173] (port=33695 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KEtNi-0003TQ-Ah for qemu-devel@nongnu.org; Fri, 04 Jul 2008 18:03:54 -0400 Received: from fmmailgate01.web.de ([217.72.192.221]:54984) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KEtNi-0006k1-9l for qemu-devel@nongnu.org; Fri, 04 Jul 2008 18:03:54 -0400 Message-ID: <486E9E48.2010308@web.de> Date: Sat, 05 Jul 2008 00:03:52 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <486CF559.5090805@siemens.com> <486CF757.3080805@siemens.com> In-Reply-To: <486CF757.3080805@siemens.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Sender: jan.kiszka@web.de Subject: [Qemu-devel] [PATCH 5/13] Introduce next_cflags - v2 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paul Brook [ Paul, this should close the interrupt window you were concerned about. ] Introduce next_cflags as part of CPUState. It controls the compile flags of the next newly generated TB. After use, it will automatically be reset to zero. This allows the caller to simply set and then forget about it, e.g. to ensure that the next, and only the next TB will contain just a single instruction. To avoid that next_cflags hits the wrong TB, interrupt delivery is suppressed while this field is non-zero. Signed-off-by: Jan Kiszka --- cpu-defs.h | 4 ++++ cpu-exec.c | 9 +++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) Index: b/cpu-defs.h =================================================================== --- a/cpu-defs.h +++ b/cpu-defs.h @@ -183,6 +183,10 @@ typedef struct CPUWatchpoint { } icount_decr; \ uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ \ + /* Compile flags for generating next regular TB. \ + Will be automatically zeroed after use. */ \ + uint16_t next_cflags; \ + \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ CPUBreakpoint *breakpoints; \ Index: b/cpu-exec.c =================================================================== --- a/cpu-exec.c +++ b/cpu-exec.c @@ -150,7 +150,8 @@ static TranslationBlock *tb_find_slow(ta } not_found: /* if no translated code available, then translate it now */ - tb = tb_gen_code(env, pc, cs_base, flags, 0); + tb = tb_gen_code(env, pc, cs_base, flags, env->next_cflags); + env->next_cflags = 0; found: /* we add the TB in the virtual pc hash table */ @@ -360,8 +361,12 @@ int cpu_exec(CPUState *env1) next_tb = 0; /* force lookup of first TB */ for(;;) { interrupt_request = env->interrupt_request; + /* Deliver interrupt, but only if we are not recompiling some + TB (non-zero next_cflags) and the current single-step mode + doesn't block IRQs. */ if (unlikely(interrupt_request) && - likely(!(env->singlestep_enabled & SSTEP_NOIRQ))) { + likely(env->next_cflags == 0 && + !(env->singlestep_enabled & SSTEP_NOIRQ))) { if (interrupt_request & CPU_INTERRUPT_DEBUG) { env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; env->exception_index = EXCP_DEBUG;