From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KJWNP-0002DG-6o for qemu-devel@nongnu.org; Thu, 17 Jul 2008 12:30:43 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KJWNN-0002D4-Qz for qemu-devel@nongnu.org; Thu, 17 Jul 2008 12:30:41 -0400 Received: from [199.232.76.173] (port=38510 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KJWNN-0002D1-Kw for qemu-devel@nongnu.org; Thu, 17 Jul 2008 12:30:41 -0400 Received: from gecko.sbs.de ([194.138.37.40]:24787) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KJWNM-000656-W0 for qemu-devel@nongnu.org; Thu, 17 Jul 2008 12:30:41 -0400 Received: from mail1.sbs.de (localhost [127.0.0.1]) by gecko.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m6HGUcLD024186 for ; Thu, 17 Jul 2008 18:30:38 +0200 Received: from [139.25.109.167] (mchn012c.mchp.siemens.de [139.25.109.167] (may be forged)) by mail1.sbs.de (8.12.11.20060308/8.12.11) with ESMTP id m6HGUc3O031601 for ; Thu, 17 Jul 2008 18:30:38 +0200 Message-ID: <487F73AE.50509@siemens.com> Date: Thu, 17 Jul 2008 18:30:38 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <487F3393.3040609@siemens.com> <487F51E1.9070102@bellard.org> In-Reply-To: <487F51E1.9070102@bellard.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: [RFC][PATCH] x86: CS limit checks Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Fabrice Bellard wrote: > Jan Kiszka wrote: >> Here is a proposal for adding code segment limit checks to x86. This >> patch should not need the -seg-checks switch as its tests are mostly >> performed during translation time. Moreover, I tried to confine the >> small additional overhead in the TB lookup procedure to x86 and Sparc. >> >> Note that this patch depends on my debugging series, namely [1], as that >> one reduces the x86-specific code passages for TB generation. Also note >> that this patch is early and only lightly tested so far, not yet >> intended for inclusion, but definitely for commenting on! > > Using more than 32 bits for cs_limit (and cs_base) in the TB is > wasteful, so I strongly suggest to use a uint32_t type. In that case, > cs_limit must be explicitely ignored in 64 bit code. > > @@ -172,6 +173,8 @@ static inline TranslationBlock *tb_find_ > flags = env->hflags; > flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); > cs_base = env->segs[R_CS].base; > + if ((env->hflags & (HF_PE_MASK | HF_CS64_MASK)) == HF_PE_MASK) > + cs_limit = env->segs[R_CS].limit; > pc = cs_base + env->eip; > > This test should be suppressed for performance reasons. Yes, the test should be moved to the translator code. This will also allow to reduce the width of cs_base/limit. > > Generally speaking as I said in a private mail, I don't want an option > -seg-checks: the segment limit and right checks must always be enabled, > even if there is a small performance hit. The way to implement it is to > store in the TB.flags for each segment whether the limit must be tested > and whether the segment is RW. Switching a segment selector is not yet a TB termination reason IIRC. I'm not sure about the implication of such a change, e.g. if there are relevant use case that have relaxed segment limits and attributes, but perform a lot segment register reloads. And then there is the open question how much performance can be gained with compile-time optimization for those guests who do use segmentation. The worst case is very roughly about 50% slowdown right now (/w vs. w/o -seg-checks). As answered privately, some -no-seg-checks switch could remain a useful optimization. Jan