From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 0/2] target/arm: Implement Cortex Neoverse-V1
Date: Tue, 4 Jul 2023 16:54:56 +0200 [thread overview]
Message-ID: <488ca2a9-8e1a-3a62-8487-fefaed69ca8b@linaro.org> (raw)
In-Reply-To: <81e6bf97-b6c6-e09d-51b5-445bdc3a47bb@linaro.org>
On 4/7/23 15:35, Marcin Juszkiewicz wrote:
> W dniu 4.07.2023 o 15:06, Peter Maydell pisze:
>
>> This patchset implements the Cortex Neoverse-V1 CPU type, as a
>> representative Armv8.3 (+ some extras from 8.4) CPU matching real
>> hardware. The main thing we were waiting for to be able to define
>> this was FEAT_LSE2, and that is now supported.
>
> Now I can add "reach SBSA level 4" to todo list as it requires v8.3 cpu
> (I do not count 'max' cpu type).
Do we need to introduce machine variants, such sbsa-lvl3-ref and
sbsa-lvl4-ref? Or simply sbsa-level3/sbsa-level4?
next prev parent reply other threads:[~2023-07-04 14:55 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 13:06 [PATCH 0/2] target/arm: Implement Cortex Neoverse-V1 Peter Maydell
2023-07-04 13:06 ` [PATCH 1/2] target/arm: Suppress more TCG unimplemented features in ID registers Peter Maydell
2023-07-04 13:45 ` Alex Bennée
2023-07-05 13:52 ` Richard Henderson
2023-07-04 13:06 ` [PATCH 2/2] target/arm: Define neoverse-v1 Peter Maydell
2023-07-04 14:58 ` Alex Bennée
2023-07-05 14:09 ` Richard Henderson
2023-07-06 12:29 ` Peter Maydell
2023-07-04 13:35 ` [PATCH 0/2] target/arm: Implement Cortex Neoverse-V1 Marcin Juszkiewicz
2023-07-04 14:54 ` Philippe Mathieu-Daudé [this message]
2023-07-04 15:00 ` Marcin Juszkiewicz
2023-07-04 15:02 ` Philippe Mathieu-Daudé
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