From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KV6CM-00070T-Ng for qemu-devel@nongnu.org; Mon, 18 Aug 2008 10:59:10 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KV6CL-0006zQ-Ds for qemu-devel@nongnu.org; Mon, 18 Aug 2008 10:59:10 -0400 Received: from [199.232.76.173] (port=53226 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KV6CL-0006zE-73 for qemu-devel@nongnu.org; Mon, 18 Aug 2008 10:59:09 -0400 Received: from ns2.suse.de ([195.135.220.15]:40498 helo=mx2.suse.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KV6CK-0007RJ-Ft for qemu-devel@nongnu.org; Mon, 18 Aug 2008 10:59:08 -0400 Received: from Relay2.suse.de (relay-ext.suse.de [195.135.221.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 35AC945DCE for ; Mon, 18 Aug 2008 16:59:07 +0200 (CEST) Message-ID: <48A98212.6050701@suse.de> Date: Mon, 18 Aug 2008 16:07:14 +0200 From: Alexander Graf MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------050904040006010000060201" Subject: [Qemu-devel] [PATCH 2/3] [x86] Core 2 Duo specification v2 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------050904040006010000060201 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch adds a Core 2 Duo CPU to the available CPU types. The CPU definition tries to resemble a real CPU as good as possible, whilst not exposing features qemu does not implement. The patch also includes some minor additions that Core 2 Duo CPUs have: - New MSR: MSR_IA32_PERF_STATUS - CPUID up to level 5 (cache info and mwait) Signed-off-by: Alexander Graf --------------050904040006010000060201 Content-Type: text/x-patch; name="se02-cpu-core2duo.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="se02-cpu-core2duo.patch" diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h index 7e95900..3c84dc9 100644 --- a/qemu/target-i386/cpu.h +++ b/qemu/target-i386/cpu.h @@ -248,6 +248,8 @@ #define MSR_MCG_STATUS 0x17a #define MSR_MCG_CTL 0x17b +#define MSR_IA32_PERF_STATUS 0x198 + #define MSR_PAT 0x277 #define MSR_EFER 0xc0000080 @@ -339,6 +341,9 @@ #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ +#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ +#define CPUID_MWAIT_EMX (0 << 1) /* enumeration supported */ + #define EXCP00_DIVZ 0 #define EXCP01_SSTP 1 #define EXCP02_NMI 2 diff --git a/qemu/target-i386/helper.c b/qemu/target-i386/helper.c index 73ce7da..0a02a90 100644 --- a/qemu/target-i386/helper.c +++ b/qemu/target-i386/helper.c @@ -173,6 +173,23 @@ static x86_def_t x86_defs[] = { .xlevel = 0x8000000A, .model_id = "QEMU Virtual CPU version " QEMU_VERSION, }, + { + .name = "core2duo", + /* original is on level 10 */ + .level = 5, + .family = 6, + .model = 15, + .stepping = 11, + /* the original CPU does have many more features that are not implemented yet */ + .features = PPRO_FEATURES | + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | + CPUID_PSE36, + .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, + .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .xlevel = 0x8000000A, + .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", + }, #endif { .name = "qemu32", diff --git a/qemu/target-i386/op_helper.c b/qemu/target-i386/op_helper.c index 0b5fdc0..781c1d5 100644 --- a/qemu/target-i386/op_helper.c +++ b/qemu/target-i386/op_helper.c @@ -1915,6 +1915,43 @@ void helper_cpuid(void) ECX = 0; EDX = 0x2c307d; break; + case 4: + /* cache info: needed for Core compatibility */ + switch (ECX) { + case 0: /* L1 dcache info */ + EAX = 0x0000121; + EBX = 0x1c0003f; + ECX = 0x000003f; + EDX = 0x0000001; + break; + case 1: /* L1 icache info */ + EAX = 0x0000122; + EBX = 0x1c0003f; + ECX = 0x000003f; + EDX = 0x0000001; + break; + case 2: /* L2 cache info */ + EAX = 0x0000143; + EBX = 0x3c0003f; + ECX = 0x0000fff; + EDX = 0x0000001; + break; + default: /* end of info */ + EAX = 0; + EBX = 0; + ECX = 0; + EDX = 0; + break; + } + + break; + case 5: + /* mwait info: needed for Core compatibility */ + EAX = 0; /* Smallest monitor-line size in bytes */ + EBX = 0; /* Largest monitor-line size in bytes */ + ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; + EDX = 0; + break; case 0x80000000: EAX = env->cpuid_xlevel; EBX = env->cpuid_vendor1; @@ -3085,6 +3150,12 @@ void helper_wrmsr(void) case MSR_VM_HSAVE_PA: env->vm_hsave = val; break; + case MSR_IA32_PERF_STATUS: + /* tsc_increment_by_tick */ + val = 1000ULL; + /* CPU multiplier */ + val |= (((uint64_t)4ULL) << 40); + break; #ifdef TARGET_X86_64 case MSR_LSTAR: env->lstar = val; --------------050904040006010000060201--