From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KWXfl-0001gA-9h for qemu-devel@nongnu.org; Fri, 22 Aug 2008 10:31:29 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KWXfj-0001fH-Dj for qemu-devel@nongnu.org; Fri, 22 Aug 2008 10:31:28 -0400 Received: from [199.232.76.173] (port=34648 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KWXfj-0001f5-6J for qemu-devel@nongnu.org; Fri, 22 Aug 2008 10:31:27 -0400 Received: from ns.suse.de ([195.135.220.2]:46463 helo=mx1.suse.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KWXfi-0002JN-NU for qemu-devel@nongnu.org; Fri, 22 Aug 2008 10:31:26 -0400 Message-ID: <48AEC18F.40707@suse.de> Date: Fri, 22 Aug 2008 15:39:27 +0200 From: Alexander Graf MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 0/3] [x86] Add Core 2 Duo CPU specification v3 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi, this set of patches attempts to implement a CPU definition set for current Intel CPUs that resembles an original as closely as currently possible. Several features a current Intel CPU has are not implemented by qemu, but that should not keep us from adding this definition so people can add features later on. As a side effect, I made the sysenter instruction 64-bit aware. This was an issue in KVM, that used the 32-bit cpu struct variables to hold 64-bit MSR values sysenter needs. I believe it to be a step in the right direction to not fix this only for KVM, but make the functionality available to qemu as well. Version 2 adds save/load. Only the sysenter implementation has changed. Version 3 pushes the series from -p2 to -p1 Alex