From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KlDs5-0004G4-P5 for qemu-devel@nongnu.org; Wed, 01 Oct 2008 22:24:53 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KlDs3-0004Fq-8z for qemu-devel@nongnu.org; Wed, 01 Oct 2008 22:24:52 -0400 Received: from [199.232.76.173] (port=41494 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KlDs3-0004Fn-3Q for qemu-devel@nongnu.org; Wed, 01 Oct 2008 22:24:51 -0400 Received: from pop-gadwall.atl.sa.earthlink.net ([207.69.195.61]:44847) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KlDs2-0002rZ-Vn for qemu-devel@nongnu.org; Wed, 01 Oct 2008 22:24:51 -0400 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=[192.168.0.90]) by pop-gadwall.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1KlDrv-0005UJ-00 for qemu-devel@nongnu.org; Wed, 01 Oct 2008 22:24:43 -0400 Message-ID: <48E430EB.5020202@earthlink.net> Date: Wed, 01 Oct 2008 22:24:43 -0400 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------090005030909090507000209" Subject: [Qemu-devel] [PATCH] sparc: show size for unassigned accesses Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------090005030909090507000209 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit --------------090005030909090507000209 Content-Type: text/plain; name="unassigned.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="unassigned.diff.txt" Index: target-sparc/cpu.h =================================================================== --- target-sparc/cpu.h (revision 5391) +++ target-sparc/cpu.h (working copy) @@ -424,7 +424,7 @@ /* cpu-exec.c */ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, - int is_asi); + int is_asi, int size); int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #define CPUState CPUSPARCState Index: target-sparc/op_helper.c =================================================================== --- target-sparc/op_helper.c (revision 5391) +++ target-sparc/op_helper.c (working copy) @@ -950,7 +950,7 @@ break; case 8: /* User code access, XXX */ default: - do_unassigned_access(addr, 0, 0, asi); + do_unassigned_access(addr, 0, 0, asi, size); ret = 0; break; } @@ -1284,7 +1284,7 @@ case 8: /* User code access, XXX */ case 9: /* Supervisor code access, XXX */ default: - do_unassigned_access(addr, 1, 0, asi); + do_unassigned_access(addr, 1, 0, asi, size); break; } #ifdef DEBUG_ASI @@ -1464,7 +1464,7 @@ case 0x8a: // Primary no-fault LE, RO case 0x8b: // Secondary no-fault LE, RO default: - do_unassigned_access(addr, 1, 0, 1); + do_unassigned_access(addr, 1, 0, 1, size); return; } } @@ -1675,7 +1675,7 @@ case 0x5f: // D-MMU demap, WO case 0x77: // Interrupt vector, WO default: - do_unassigned_access(addr, 0, 0, 1); + do_unassigned_access(addr, 0, 0, 1, size); ret = 0; break; } @@ -2082,7 +2082,7 @@ case 0x8a: // Primary no-fault LE, RO case 0x8b: // Secondary no-fault LE, RO default: - do_unassigned_access(addr, 1, 0, 1); + do_unassigned_access(addr, 1, 0, 1, size); return; } } @@ -3025,7 +3025,7 @@ #ifndef TARGET_SPARC64 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, - int is_asi) + int is_asi, int size) { CPUState *saved_env; @@ -3035,14 +3035,15 @@ env = cpu_single_env; #ifdef DEBUG_UNASSIGNED if (is_asi) - printf("Unassigned mem %s access to " TARGET_FMT_plx + printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx " asi 0x%02x from " TARGET_FMT_lx "\n", - is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi, - env->pc); + is_exec ? "exec" : is_write ? "write" : "read", size, + size == 1 ? "" : "s", addr, is_asi, env->pc); else - printf("Unassigned mem %s access to " TARGET_FMT_plx " from " - TARGET_FMT_lx "\n", - is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc); + printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx + " from " TARGET_FMT_lx "\n", + is_exec ? "exec" : is_write ? "write" : "read", size, + size == 1 ? "" : "s", addr, env->pc); #endif if (env->mmuregs[3]) /* Fault status register */ env->mmuregs[3] = 1; /* overflow (not read before another fault) */ @@ -3066,7 +3067,7 @@ } #else void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, - int is_asi) + int is_asi, int size) { #ifdef DEBUG_UNASSIGNED CPUState *saved_env; Index: exec.c =================================================================== --- exec.c (revision 5391) +++ exec.c (working copy) @@ -2290,35 +2290,85 @@ printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif #ifdef TARGET_SPARC + do_unassigned_access(addr, 0, 0, 0, 1); +#elif defined(TARGET_CRIS) do_unassigned_access(addr, 0, 0, 0); +#endif + return 0; +} + +static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) +{ +#ifdef DEBUG_UNASSIGNED + printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); +#endif +#ifdef TARGET_SPARC + do_unassigned_access(addr, 0, 0, 0, 2); #elif defined(TARGET_CRIS) do_unassigned_access(addr, 0, 0, 0); #endif return 0; } +static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) +{ +#ifdef DEBUG_UNASSIGNED + printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); +#endif +#ifdef TARGET_SPARC + do_unassigned_access(addr, 0, 0, 0, 4); +#elif defined(TARGET_CRIS) + do_unassigned_access(addr, 0, 0, 0); +#endif + return 0; +} + static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); #endif #ifdef TARGET_SPARC + do_unassigned_access(addr, 1, 0, 0, 1); +#elif defined(TARGET_CRIS) do_unassigned_access(addr, 1, 0, 0); +#endif +} + +static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +{ +#ifdef DEBUG_UNASSIGNED + printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); +#endif +#ifdef TARGET_SPARC + do_unassigned_access(addr, 1, 0, 0, 2); #elif defined(TARGET_CRIS) do_unassigned_access(addr, 1, 0, 0); #endif } +static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +{ +#ifdef DEBUG_UNASSIGNED + printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); +#endif +#ifdef TARGET_SPARC + do_unassigned_access(addr, 1, 0, 0, 4); +#elif defined(TARGET_CRIS) + do_unassigned_access(addr, 1, 0, 0); +#endif +} + static CPUReadMemoryFunc *unassigned_mem_read[3] = { unassigned_mem_readb, - unassigned_mem_readb, - unassigned_mem_readb, + unassigned_mem_readw, + unassigned_mem_readl, }; static CPUWriteMemoryFunc *unassigned_mem_write[3] = { unassigned_mem_writeb, - unassigned_mem_writeb, - unassigned_mem_writeb, + unassigned_mem_writew, + unassigned_mem_writel, }; static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, Index: exec-all.h =================================================================== --- exec-all.h (revision 5391) +++ exec-all.h (working copy) @@ -330,7 +330,9 @@ } pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { -#if defined(TARGET_SPARC) || defined(TARGET_MIPS) +#if defined(TARGET_SPARC) + do_unassigned_access(addr, 0, 1, 0, 4); +#elif defined(TARGET_MIPS) do_unassigned_access(addr, 0, 1, 0); #else cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); --------------090005030909090507000209--