From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KlQUk-0000za-UZ for qemu-devel@nongnu.org; Thu, 02 Oct 2008 11:53:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KlQUi-0000yu-Pg for qemu-devel@nongnu.org; Thu, 02 Oct 2008 11:53:37 -0400 Received: from [199.232.76.173] (port=57159 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KlQUi-0000yp-Mv for qemu-devel@nongnu.org; Thu, 02 Oct 2008 11:53:36 -0400 Received: from mail-gx0-f19.google.com ([209.85.217.19]:63326) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KlQUi-00005m-CN for qemu-devel@nongnu.org; Thu, 02 Oct 2008 11:53:36 -0400 Received: by gxk12 with SMTP id 12so1660565gxk.10 for ; Thu, 02 Oct 2008 08:53:35 -0700 (PDT) Message-ID: <48E4EE3D.2090503@codemonkey.ws> Date: Thu, 02 Oct 2008 10:52:29 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 4/4] pci: use pci_config_header in pci.c References: <1222870375-13489-1-git-send-email-kraxel@redhat.com> <1222870375-13489-4-git-send-email-kraxel@redhat.com> <48E3A5BD.8010000@codemonkey.ws> <48E3CAF9.5040207@redhat.com> <48E3CF33.3050702@codemonkey.ws> <48E47E93.5000605@redhat.com> In-Reply-To: <48E47E93.5000605@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: qemu-devel@nongnu.org, Paul Brook Gerd Hoffmann wrote: > Anthony Liguori wrote: > >> Because the config structure is loaded after pci_register device and >> because the MMIO callbacks into the config space? If you look at >> pci_default_read_config(), it actually does conversion from le to host >> CPU because that's what MMIO callbacks expect. >> > > Yep. > > >> If you simply removed >> this, it would work. >> > > Ah, *now* I see what you mean. > > Well. That assumes the guests always use the correct in{b,w,l} > instruction to access the config space values, i.e. never ever try to > use two inb reads for a 16bit value for example. Or a inw for the lower > 16 bits of a 32bit value because they know the high bits are zero anyway. > > I have my doubts that this is a sane expectation. > The config space seems organized by data size so you could always just take care of this in the accessors. That is, if you get a byte access to a 32-bit value, you would do something like: (cpu_to_le32(d->config + (addr & ~3)) >> (8 * (addr % 4))) & 0xFF; Not the prettiest thing in the world, but it would work. >> Of course, you'll have to audit each caller of >> pci_register_device() and make sure their config's get changed too. >> > > Sure, that would be a *big* task & patch. > Actually, it's not. I did a quick grep, noone seems to pass in a config_read accessor. Only config_write is ever passed and it only seems to be to used to add callbacks when particular config values are written. pci_default_config_write is still used to do the actual write. Regards, Anthony Liguori > cheers, > Gerd > > >