From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KlUPY-0003KZ-2S for qemu-devel@nongnu.org; Thu, 02 Oct 2008 16:04:32 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KlUPV-0003JK-OK for qemu-devel@nongnu.org; Thu, 02 Oct 2008 16:04:30 -0400 Received: from [199.232.76.173] (port=46590 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KlUPU-0003J8-NE for qemu-devel@nongnu.org; Thu, 02 Oct 2008 16:04:28 -0400 Received: from moutng.kundenserver.de ([212.227.126.171]:49284) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KlUPT-0006Ca-RU for qemu-devel@nongnu.org; Thu, 02 Oct 2008 16:04:28 -0400 Message-ID: <48E5294A.8090209@mail.berlios.de> Date: Thu, 02 Oct 2008 22:04:26 +0200 From: Stefan Weil MIME-Version: 1.0 Subject: [Qemu-devel] [PATCH] Add support for CPU_LOG_INT (MIPS targets) Content-Type: multipart/mixed; boundary="------------090006010909060203020400" Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Developers This is a multi-part message in MIME format. --------------090006010909060203020400 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit This patch adds some interrupt logging for MIPS targets. Please apply it to Qemu trunk. Regards Stefan --------------090006010909060203020400 Content-Type: text/x-diff; name="mips_int.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="mips_int.patch" Add interrupt logging for MIPS targets. Signed-off-by: Stefan Weil Index: hw/mips_int.c =================================================================== --- hw/mips_int.c (Revision 5400) +++ hw/mips_int.c (Arbeitskopie) @@ -1,6 +1,7 @@ #include "hw.h" #include "mips.h" #include "cpu.h" +#include "qemu-log.h" /* Raise IRQ to CPU if necessary. It must be called every time the active IRQ may change */ @@ -12,10 +13,28 @@ !(env->hflags & MIPS_HFLAG_DM)) { if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && !(env->interrupt_request & CPU_INTERRUPT_HARD)) { + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: cpu_interrupt (0x%08x,0x%08x)\n", __func__, + env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask, + env->interrupt_request); + cpu_dump_state(env, logfile, fprintf, 0); + } cpu_interrupt(env, CPU_INTERRUPT_HARD); - } - } else + } else { + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: no interrupt (0x%08x,0x%08x)\n", __func__, + env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask, + env->interrupt_request); + cpu_dump_state(env, logfile, fprintf, 0); + } + } + } else { + if (loglevel & CPU_LOG_INT) { + fprintf(logfile, "%s: cpu_reset_interrupt\n", __func__); + cpu_dump_state(env, logfile, fprintf, 0); + } cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + } } static void cpu_mips_irq_request(void *opaque, int irq, int level) --------------090006010909060203020400--