From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KpneL-000186-1C for qemu-devel@nongnu.org; Tue, 14 Oct 2008 13:25:37 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KpneJ-00017h-PN for qemu-devel@nongnu.org; Tue, 14 Oct 2008 13:25:36 -0400 Received: from [199.232.76.173] (port=46704 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KpneJ-00017e-Fa for qemu-devel@nongnu.org; Tue, 14 Oct 2008 13:25:35 -0400 Received: from moutng.kundenserver.de ([212.227.126.187]:51682) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KpneI-0002mL-RS for qemu-devel@nongnu.org; Tue, 14 Oct 2008 13:25:35 -0400 Message-ID: <48F4D60A.9050309@mail.berlios.de> Date: Tue, 14 Oct 2008 19:25:30 +0200 From: Stefan Weil MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] Add support for CPU_LOG_INT (MIPS targets) References: <48E5294A.8090209@mail.berlios.de> <20081014095802.GB13141@volta.aurel32.net> In-Reply-To: <20081014095802.GB13141@volta.aurel32.net> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: QEMU Developers Aurelien Jarno schrieb: > On Thu, Oct 02, 2008 at 10:04:26PM +0200, Stefan Weil wrote: > > ... >> Add interrupt logging for MIPS targets. >> >> Signed-off-by: Stefan Weil >> >> Index: hw/mips_int.c >> =================================================================== >> --- hw/mips_int.c (Revision 5400) >> +++ hw/mips_int.c (Arbeitskopie) >> @@ -1,6 +1,7 @@ >> #include "hw.h" >> #include "mips.h" >> #include "cpu.h" >> +#include "qemu-log.h" >> >> /* Raise IRQ to CPU if necessary. It must be called every time the active >> IRQ may change */ >> @@ -12,10 +13,28 @@ >> !(env->hflags & MIPS_HFLAG_DM)) { >> if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && >> !(env->interrupt_request & CPU_INTERRUPT_HARD)) { >> + if (loglevel & CPU_LOG_INT) { >> + fprintf(logfile, "%s: cpu_interrupt (0x%08x,0x%08x)\n", __func__, >> + env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask, >> + env->interrupt_request); >> + cpu_dump_state(env, logfile, fprintf, 0); >> + } >> cpu_interrupt(env, CPU_INTERRUPT_HARD); >> - } >> - } else >> + } else { >> + if (loglevel & CPU_LOG_INT) { >> + fprintf(logfile, "%s: no interrupt (0x%08x,0x%08x)\n", __func__, >> + env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask, >> + env->interrupt_request); >> + cpu_dump_state(env, logfile, fprintf, 0); >> + } >> > > I am not sure we really want to log this case, as no interrupt are > actually triggered (disabled interrupt, already processing an > interrupt, etc.) > Well, I added this code to debug a real problem, not just for fun. It helps to see who triggers this code, even when interrupts are disabled at that moment. >> + } >> + } else { >> + if (loglevel & CPU_LOG_INT) { >> + fprintf(logfile, "%s: cpu_reset_interrupt\n", __func__); >> + cpu_dump_state(env, logfile, fprintf, 0); >> + } >> cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); >> + } >> } >> >> static void cpu_mips_irq_request(void *opaque, int irq, int level) >> > > Otherwise looks ok. > > Thanks, Stefan