From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH][ppc] reorganize register set for SPE + TCG
Date: Wed, 15 Oct 2008 18:11:30 +0200 [thread overview]
Message-ID: <48F61632.2090300@aurel32.net> (raw)
In-Reply-To: <20081015142237.GN18389@codesourcery.com>
Nathan Froyd a écrit :
> The (large, invasive) patch below is a preparation patch for converting
> (most) SPE instructions to use TCG. The rationale is that your ordinary
> SPE instruction deals with three 64-bit quantaties (and a potential
> 64-bit accumulator). In the current implementation, it's extremely
> laborious/difficult to pass those 64-bit quantaties to helpers, since
> the high/low words for SPE registers are not contiguous in the
> environment. (TCG helpers for SPE instructions are not yet implemented,
> but they will be necessary as part of the total conversion to TCG.)
You can pass 64-bit TCG registers to helpers. And you can create one TCG
64-bit value from two 32-bits value if needed, and split it back later.
This is exactly what is already done with load_gpr64() and store_gpr64().
Then the limit on the number of arguments of TCG helpers is not a
problem anymore.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
prev parent reply other threads:[~2008-10-15 16:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-15 14:22 [Qemu-devel] [PATCH][ppc] reorganize register set for SPE + TCG Nathan Froyd
2008-10-15 15:20 ` Nathan Froyd
2008-10-15 15:25 ` Paul Brook
2008-10-15 16:11 ` Aurelien Jarno [this message]
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