Re: [Qemu-devel] [PATCH][ppc] convert SPE logical instructions to TCG

[Aurelien Jarno <aurelien@aurel32.net>]

Nathan Froyd a écrit :
> On Tue, Oct 14, 2008 at 09:16:17PM +0200, Aurelien Jarno wrote:
>> Yes, you should use local variable, cpu_T array will eventually
>> disappear. However, I am more concerned by the fact that it may not be a
>> good idea to expand the macro. IMHO you should put the common code in 
>> the macro and pass the name of the function that does the logical
>> operation as an argument.

Applied with the change suggested by Paul Brook. Thanks.

> Done thusly.
> 
> -Nathan
> 
> diff -r 5ed4e3fd0fe7 -r cac4af009435 target-ppc/op.c
> --- a/target-ppc/op.c	Tue Oct 14 15:23:35 2008 -0400
> +++ b/target-ppc/op.c	Tue Oct 14 22:06:28 2008 -0400
> @@ -2513,54 +2513,6 @@
>      RETURN();
>  }
>  
> -void OPPROTO op_evand (void)
> -{
> -    T0_64 &= T1_64;
> -    RETURN();
> -}
> -
> -void OPPROTO op_evandc (void)
> -{
> -    T0_64 &= ~T1_64;
> -    RETURN();
> -}
> -
> -void OPPROTO op_evor (void)
> -{
> -    T0_64 |= T1_64;
> -    RETURN();
> -}
> -
> -void OPPROTO op_evxor (void)
> -{
> -    T0_64 ^= T1_64;
> -    RETURN();
> -}
> -
> -void OPPROTO op_eveqv (void)
> -{
> -    T0_64 = ~(T0_64 ^ T1_64);
> -    RETURN();
> -}
> -
> -void OPPROTO op_evnor (void)
> -{
> -    T0_64 = ~(T0_64 | T1_64);
> -    RETURN();
> -}
> -
> -void OPPROTO op_evorc (void)
> -{
> -    T0_64 |= ~T1_64;
> -    RETURN();
> -}
> -
> -void OPPROTO op_evnand (void)
> -{
> -    T0_64 = ~(T0_64 & T1_64);
> -    RETURN();
> -}
> -
>  void OPPROTO op_evsrws (void)
>  {
>      do_evsrws();
> diff -r 5ed4e3fd0fe7 -r cac4af009435 target-ppc/translate.c
> --- a/target-ppc/translate.c	Tue Oct 14 15:23:35 2008 -0400
> +++ b/target-ppc/translate.c	Tue Oct 14 22:06:28 2008 -0400
> @@ -5427,6 +5427,23 @@
>      gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);                             \
>  }
>  
> +#define GEN_SPEOP_TCG_ARITH2(name)                                            \
> +static always_inline void gen_##name (DisasContext *ctx)                      \
> +{                                                                             \
> +    if (unlikely(!ctx->spe_enabled)) {                                        \
> +        GEN_EXCP_NO_AP(ctx);                                                  \
> +        return;                                                               \
> +    }                                                                         \
> +    TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64);                               \
> +    TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64);                               \
> +    gen_load_gpr64(t0, rA(ctx->opcode));                                      \
> +    gen_load_gpr64(t1, rB(ctx->opcode));                                      \
> +    gen_op_##name(t0, t1);                                                    \
> +    gen_store_gpr64(rD(ctx->opcode), t0);                                     \
> +    tcg_temp_free(t0);                                                        \
> +    tcg_temp_free(t1);                                                        \
> +}
> +
>  #define GEN_SPEOP_ARITH1(name)                                                \
>  static always_inline void gen_##name (DisasContext *ctx)                      \
>  {                                                                             \
> @@ -5453,14 +5470,59 @@
>  }
>  
>  /* Logical */
> -GEN_SPEOP_ARITH2(evand);
> -GEN_SPEOP_ARITH2(evandc);
> -GEN_SPEOP_ARITH2(evxor);
> -GEN_SPEOP_ARITH2(evor);
> -GEN_SPEOP_ARITH2(evnor);
> -GEN_SPEOP_ARITH2(eveqv);
> -GEN_SPEOP_ARITH2(evorc);
> -GEN_SPEOP_ARITH2(evnand);
> +static always_inline void gen_op_evand (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_and_i64(t0, t0, t1);
> +}
> +
> +static always_inline void gen_op_evandc (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_not_i64(t1, t1);
> +    tcg_gen_and_i64(t0, t0, t1);
> +}
> +
> +static always_inline void gen_op_evxor (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_xor_i64(t0, t0, t1);
> +}
> +
> +static always_inline void gen_op_evor (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_or_i64(t0, t0, t1);
> +}
> +
> +static always_inline void gen_op_evnor (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_or_i64(t0, t0, t1);
> +    tcg_gen_not_i64(t0, t0);
> +}
> +
> +static always_inline void gen_op_eveqv (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_xor_i64(t0, t0, t1);
> +    tcg_gen_not_i64(t0, t0);
> +}
> +
> +static always_inline void gen_op_evorc (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_not_i64(t1, t1);
> +    tcg_gen_or_i64(t0, t0, t1);
> +}
> +
> +static always_inline void gen_op_evnand (TCGv t0, TCGv t1)
> +{
> +    tcg_gen_and_i64(t0, t0, t1);
> +    tcg_gen_not_i64(t0, t0);
> +}
> +
> +GEN_SPEOP_TCG_ARITH2(evand);
> +GEN_SPEOP_TCG_ARITH2(evandc);
> +GEN_SPEOP_TCG_ARITH2(evxor);
> +GEN_SPEOP_TCG_ARITH2(evor);
> +GEN_SPEOP_TCG_ARITH2(evnor);
> +GEN_SPEOP_TCG_ARITH2(eveqv);
> +GEN_SPEOP_TCG_ARITH2(evorc);
> +GEN_SPEOP_TCG_ARITH2(evnand);
>  GEN_SPEOP_ARITH2(evsrwu);
>  GEN_SPEOP_ARITH2(evsrws);
>  GEN_SPEOP_ARITH2(evslw);
> 
> 
> 


-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net