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Wed, 16 Apr 2025 11:59:44 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c33fe6e1dsm17783645ad.236.2025.04.16.11.59.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Apr 2025 11:59:44 -0700 (PDT) Message-ID: <48a155a6-accb-4086-b15c-f261ce5c326d@linaro.org> Date: Wed, 16 Apr 2025 11:59:43 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 123/163] tcg: Add tcg_gen_addcio_{i32,i64,tl} Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-124-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250415192515.232910-124-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/25 12:24, Richard Henderson wrote: > Create a function for performing an add with carry-in > and producing carry out. The carry-out result is boolean. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg-op-common.h | 4 ++ > include/tcg/tcg-op.h | 2 + > tcg/tcg-op.c | 95 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 101 insertions(+) > > diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h > index 009e2778c5..b439bdb385 100644 > --- a/include/tcg/tcg-op-common.h > +++ b/include/tcg/tcg-op-common.h > @@ -135,6 +135,8 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, > TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); > void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, > TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); > +void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, > + TCGv_i32 a, TCGv_i32 b, TCGv_i32 ci); > void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); > void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); > void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); > @@ -238,6 +240,8 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, > TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); > void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, > TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); > +void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co, > + TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci); > void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); > void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); > void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); > diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h > index a02850583b..44914e9326 100644 > --- a/include/tcg/tcg-op.h > +++ b/include/tcg/tcg-op.h > @@ -252,6 +252,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) > #define tcg_gen_movcond_tl tcg_gen_movcond_i64 > #define tcg_gen_add2_tl tcg_gen_add2_i64 > #define tcg_gen_sub2_tl tcg_gen_sub2_i64 > +#define tcg_gen_addcio_tl tcg_gen_addcio_i64 > #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 > #define tcg_gen_muls2_tl tcg_gen_muls2_i64 > #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 > @@ -370,6 +371,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) > #define tcg_gen_movcond_tl tcg_gen_movcond_i32 > #define tcg_gen_add2_tl tcg_gen_add2_i32 > #define tcg_gen_sub2_tl tcg_gen_sub2_i32 > +#define tcg_gen_addcio_tl tcg_gen_addcio_i32 > #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 > #define tcg_gen_muls2_tl tcg_gen_muls2_i32 > #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 > diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c > index 447b0ebacd..b0a29278ab 100644 > --- a/tcg/tcg-op.c > +++ b/tcg/tcg-op.c > @@ -1123,6 +1123,33 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, > } > } > > +void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, > + TCGv_i32 a, TCGv_i32 b, TCGv_i32 ci) > +{ > + if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I32, 0)) { > + TCGv_i32 t0 = tcg_temp_ebb_new_i32(); > + TCGv_i32 zero = tcg_constant_i32(0); > + TCGv_i32 mone = tcg_constant_i32(-1); > + > + tcg_gen_op3_i32(INDEX_op_addco, t0, ci, mone); > + tcg_gen_op3_i32(INDEX_op_addcio, r, a, b); > + tcg_gen_op3_i32(INDEX_op_addci, co, zero, zero); > + tcg_temp_free_i32(t0); > + } else { > + TCGv_i32 t0 = tcg_temp_ebb_new_i32(); > + TCGv_i32 t1 = tcg_temp_ebb_new_i32(); > + > + tcg_gen_add_i32(t0, a, b); > + tcg_gen_setcond_i32(TCG_COND_LTU, t1, t0, a); > + tcg_gen_add_i32(r, t0, ci); > + tcg_gen_setcond_i32(TCG_COND_LTU, t0, r, t0); > + tcg_gen_or_i32(co, t0, t1); > + > + tcg_temp_free_i32(t0); > + tcg_temp_free_i32(t1); > + } > +} > + > void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, > TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) > { > @@ -2868,6 +2895,74 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, > } > } > > +void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co, > + TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci) > +{ > + if (TCG_TARGET_REG_BITS == 64) { > + if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I64, 0)) { > + TCGv_i64 discard = tcg_temp_ebb_new_i64(); > + TCGv_i64 zero = tcg_constant_i64(0); > + TCGv_i64 mone = tcg_constant_i64(-1); > + > + tcg_gen_op3_i64(INDEX_op_addco, discard, ci, mone); > + tcg_gen_op3_i64(INDEX_op_addcio, r, a, b); > + tcg_gen_op3_i64(INDEX_op_addci, co, zero, zero); > + tcg_temp_free_i64(discard); > + } else { > + TCGv_i64 t0 = tcg_temp_ebb_new_i64(); > + TCGv_i64 t1 = tcg_temp_ebb_new_i64(); > + > + tcg_gen_add_i64(t0, a, b); > + tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, a); > + tcg_gen_add_i64(r, t0, ci); > + tcg_gen_setcond_i64(TCG_COND_LTU, t0, r, t0); > + tcg_gen_or_i64(co, t0, t1); > + > + tcg_temp_free_i64(t0); > + tcg_temp_free_i64(t1); > + } > + } else { > + if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I32, 0)) { > + TCGv_i32 discard = tcg_temp_ebb_new_i32(); > + TCGv_i32 zero = tcg_constant_i32(0); > + TCGv_i32 mone = tcg_constant_i32(-1); > + > + tcg_gen_op3_i32(INDEX_op_addco, discard, TCGV_LOW(ci), mone); > + tcg_gen_op3_i32(INDEX_op_addcio, discard, TCGV_HIGH(ci), mone); > + tcg_gen_op3_i32(INDEX_op_addcio, TCGV_LOW(r), > + TCGV_LOW(a), TCGV_LOW(b)); > + tcg_gen_op3_i32(INDEX_op_addcio, TCGV_HIGH(r), > + TCGV_HIGH(a), TCGV_HIGH(b)); > + tcg_gen_op3_i32(INDEX_op_addci, TCGV_LOW(co), zero, zero); > + tcg_temp_free_i32(discard); > + } else { > + TCGv_i32 t0 = tcg_temp_ebb_new_i32(); > + TCGv_i32 c0 = tcg_temp_ebb_new_i32(); > + TCGv_i32 c1 = tcg_temp_ebb_new_i32(); > + > + tcg_gen_or_i32(c1, TCGV_LOW(ci), TCGV_HIGH(ci)); > + tcg_gen_setcondi_i32(TCG_COND_NE, c1, c1, 0); > + > + tcg_gen_add_i32(t0, TCGV_LOW(a), TCGV_LOW(b)); > + tcg_gen_setcond_i32(TCG_COND_LTU, c0, t0, TCGV_LOW(a)); > + tcg_gen_add_i32(TCGV_LOW(r), t0, c1); > + tcg_gen_setcond_i32(TCG_COND_LTU, c1, TCGV_LOW(r), c1); > + tcg_gen_or_i32(c1, c1, c0); > + > + tcg_gen_add_i32(t0, TCGV_HIGH(a), TCGV_HIGH(b)); > + tcg_gen_setcond_i32(TCG_COND_LTU, c0, t0, TCGV_HIGH(a)); > + tcg_gen_add_i32(TCGV_HIGH(r), t0, c1); > + tcg_gen_setcond_i32(TCG_COND_LTU, c1, TCGV_HIGH(r), c1); > + tcg_gen_or_i32(TCGV_LOW(co), c0, c1); > + > + tcg_temp_free_i32(t0); > + tcg_temp_free_i32(c0); > + tcg_temp_free_i32(c1); > + } > + tcg_gen_movi_i32(TCGV_HIGH(co), 0); > + } > +} > + > void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, > TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) > { Reviewed-by: Pierrick Bouvier