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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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Date: Wed, 31 Oct 2018 11:47:12 +0100
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Subject: Re: [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns
 to decodetree
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To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org


On 10/31/18 11:44 AM, Bastian Koppelmann wrote:
>
> On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
> [...]
>> +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, 
>> uint32_t insn)
>> +{
>> +#if defined(TARGET_RISCV64)
>> +    REQUIRE_FPU;
>> +
>> +    TCGv t0 = tcg_temp_new();
>> +    gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
>> +    gen_set_gpr(a->rd, t0);
>> +    tcg_temp_free(t0);
>> +#else
>> +    gen_exception_illegal(ctx);
>> +#endif
>> +    return true;
>> +}
>
>
> I'm a bit confused here. According to the spec fclass_d is a RV32F 
> instruction but according to the original qemu code it is not?


I meant RV32D, of course...