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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28b76fsm163395515e9.28.2024.11.18.05.45.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Nov 2024 05:45:52 -0800 (PST) Message-ID: <48bb0455-7c2e-4cc6-aa15-ebe4311d8430@redhat.com> Date: Mon, 18 Nov 2024 14:45:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 4/5] hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes Content-Language: en-US To: Shameerali Kolothum Thodi , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "ddutile@redhat.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" References: <20241108125242.60136-1-shameerali.kolothum.thodi@huawei.com> <20241108125242.60136-5-shameerali.kolothum.thodi@huawei.com> <1dcea5ca-806f-4f51-8b13-faf5d62eb086@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.142, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 11/18/24 12:44, Shameerali Kolothum Thodi wrote: > >> -----Original Message----- >> From: Eric Auger >> Sent: Monday, November 18, 2024 10:02 AM >> To: Shameerali Kolothum Thodi >> ; qemu-arm@nongnu.org; >> qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com; >> ddutile@redhat.com; Linuxarm ; Wangzhou (B) >> ; jiangkunkun ; >> Jonathan Cameron ; >> zhangfei.gao@linaro.org >> Subject: Re: [RFC PATCH 4/5] hw/arm/virt-acpi-build: Build IORT with >> multiple SMMU nodes >> >>> /* Number of IORT Nodes */ >>> @@ -342,10 +356,9 @@ build_iort(GArray *table_data, BIOSLinker >> *linker, VirtMachineState *vms) >>> /* GIC ITS Identifier Array */ >>> build_append_int_noprefix(table_data, 0 /* MADT translation_id */, >> 4); >>> - if (vms->iommu == VIRT_IOMMU_SMMUV3) { >>> - int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; >>> + for (i = 0; i < num_smmus; i++) { >>> + smmu_offset[i] = table_data->len - table.table_offset; >>> >> I would have expected changes in the smmu idmap has well. If a given >> SMMU instance now protects a given bus hierarchy shouldn't it be >> reflected in a differentiated SMMU idmap for each of them (RID subset of >> SMMU->pci-bus mapping to a specific IORT SMMU node)? How is it done >> currently? > I thought that smmu_idmaps will be handled by this ? > > object_child_foreach_recursive(object_get_root(), > iort_host_bridges, smmu_idmaps); to me this traverses the qemu object hierarchy to find all host bridges and for each of them builds an idmap array (smmu_idmaps mapping this RC RID range to this SMMU). But to me those idmaps will be assigned to *all* SMMU insteaces leading to a wong IORT description because all SMMUs will be protecting all devices. You shall only retain idmaps which correspond to the pci_bus a given vSMMU is attached to. Then each SMMU will protect a distinct PCIe subtree which does not seem the case today. At least that's my current understanding. Eric > > But it is possible that, there is a bug in this IORT generation here as I am not > able to hot add devices. It looks like the pciehp interrupt is not generated/received > for some reason. Nicolin[0] is suspecting the min/max bus range in > iort_host_bridges() may not leave enough ranges for hot add later. > > Cold plugging devices to different SMMUv3/pcie-pxb seems to be alright. > > I will debug that soon. > > Thanks, > Shameer > [0] https://lore.kernel.org/qemu-devel/ZzPd1F%2FUA2MKMbwl@Asurada-Nvidia/ > >