[Qemu-devel] [PATCH 2/2] Add code to override IRQ 0 to INTI 2

[Qemu-devel] [PATCH 2/2] Add code to override IRQ 0 to INTI 2

[Beth Kon]

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This patch, provided by Anthony Liguori, maps IRQ0 to INTI2.

-- 
Elizabeth Kon (Beth)
IBM Linux Technology Center
Open Hypervisor Team
email: eak@us.ibm.com

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Signed-off-by Beth Kon <bkon@us.ibm.com>

diff --git a/hw/apic.c b/hw/apic.c
index a2915f8..3e34132 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -945,6 +945,13 @@ void ioapic_set_irq(void *opaque, int vector, int level)
 {
     IOAPICState *s = opaque;
 
+    /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
+       to GSI 2.  GSI maps to ioapic 1-1.  This is not
+       the cleanest way of doing it but it should work. */
+
+    if (vector == 0)
+        vector = 2;
+
     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
         uint32_t mask = 1 << vector;
         uint64_t entry = s->ioredtbl[vector];

Re: [Qemu-devel] [PATCH 2/2] Add code to override IRQ 0 to INTI 2

[Avi Kivity]

Beth Kon wrote:
> This patch, provided by Anthony Liguori, maps IRQ0 to INTI2.
>
>   

This will cause problems for kvm, which maps interrupts 1:1 without 
exceptions.  While we could add support for remapping, it would mean 
that older kernels would not be able to support an hpet.

Isn't it possible to connect the hpet to pic irq 2 and ioapic irq 2, 
maintaining the 1:1 mapping?

(what's irq 2 connected to now?)

-- 
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.

Re: [Qemu-devel] [PATCH 2/2] Add code to override IRQ 0 to INTI 2

[Anthony Liguori]

Avi Kivity wrote:
> Beth Kon wrote:
>> This patch, provided by Anthony Liguori, maps IRQ0 to INTI2.
>>
>>   
>
> This will cause problems for kvm, which maps interrupts 1:1 without 
> exceptions.  While we could add support for remapping, it would mean 
> that older kernels would not be able to support an hpet.
>
> Isn't it possible to connect the hpet to pic irq 2 and ioapic irq 2, 
> maintaining the 1:1 mapping?

The APIC spec says that the hpet must be connected to APIC IRQ 0 and 
IOAPIC IRQ 2.  I don't understand GSI very well, but I think this is the 
normally remapping of interrupts that would occur as opposed to 
something device specific.

Regards,

Anthony Liguori

> (what's irq 2 connected to now?)
>

Re: [Qemu-devel] [PATCH 2/2] Add code to override IRQ 0 to INTI 2

[Beth Kon]

On Mon, 2008-10-27 at 14:52 -0500, Anthony Liguori wrote:
> Avi Kivity wrote:
> > Beth Kon wrote:
> >> This patch, provided by Anthony Liguori, maps IRQ0 to INTI2.
> >>
> >>   
> >
> > This will cause problems for kvm, which maps interrupts 1:1 without 
> > exceptions.  While we could add support for remapping, it would mean 
> > that older kernels would not be able to support an hpet.
> >
> > Isn't it possible to connect the hpet to pic irq 2 and ioapic irq 2, 
> > maintaining the 1:1 mapping?
> 
> The APIC spec says that the hpet must be connected to APIC IRQ 0 and 
> IOAPIC IRQ 2.  I don't understand GSI very well, but I think this is the 
> normally remapping of interrupts that would occur as opposed to 
> something device specific.
> 
Just a slight clarification to Anthony's words in order to avoid
confusion... The HPET spec says that the hpet, when replacing the PIT in
legacy mode must map to PIC IRQ 0 and APIC IRQ2.

> Regards,
> 
> Anthony Liguori
> 
> > (what's irq 2 connected to now?)
> >
> 
-- 
Elizabeth Kon (Beth)
IBM Linux Technology Center
Open Hypervisor Team
email: eak@us.ibm.com

Re: [Qemu-devel] [PATCH 2/2] Add code to override IRQ 0 to INTI 2

[Avi Kivity]

Anthony Liguori wrote:
>
> The APIC spec says that the hpet must be connected to APIC IRQ 0 and 
> IOAPIC IRQ 2.  I don't understand GSI very well, but I think this is 
> the normally remapping of interrupts that would occur as opposed to 
> something device specific.

Well the kvm irqchip doesn't support this, so it looks like we'll need 
to implement this and disable hpet for host kernels older than 2.6.29.

-- 
error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH 2/2] Add code to override IRQ 0 to INTI 2

[Avi Kivity]

Avi Kivity wrote:
>
> (what's irq 2 connected to now?)
>

Oh, of course irq 2 is only available on the ioapic; on the pic it is 
used for cascading.

If we can't find a free interrupt, we can always connect it to interrupt 
5; that will reduce the number of pci interrupts to two.  But we can 
implement apic mode and use lines 16-23 (if we add another ioapic, 16-47).

-- 
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.