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Fri, 03 May 2024 07:58:13 -0700 (PDT) Message-ID: <4906224c-b37e-4480-adc7-362ad2023b36@linaro.org> Date: Fri, 3 May 2024 16:58:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: Restrict translation disabled alignment check to VMSA To: Richard Henderson , qemu-devel@nongnu.org Cc: =?UTF-8?Q?Cl=C3=A9ment_Chigot?= , qemu-stable@nongnu.org References: <20240424170908.759043-1-richard.henderson@linaro.org> <20240424170908.759043-2-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240424170908.759043-2-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 24/4/24 19:09, Richard Henderson wrote: > For cpus using PMSA, when the MPU is disabled, the default memory > type is Normal, Non-cachable. > > Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") > Reported-by: Clément Chigot > Signed-off-by: Richard Henderson > --- > > Since v9 will likely be tagged tomorrow without this fixed, > Cc: qemu-stable@nongnu.org > > --- > target/arm/tcg/hflags.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c > index 5da1b0fc1d..66de30b828 100644 > --- a/target/arm/tcg/hflags.c > +++ b/target/arm/tcg/hflags.c > @@ -38,8 +38,16 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) > } > > /* > - * If translation is disabled, then the default memory type is > - * Device(-nGnRnE) instead of Normal, which requires that alignment > + * With PMSA, when the MPU is disabled, all memory types in the > + * default map is Normal. > + */ > + if (arm_feature(env, ARM_FEATURE_PMSA)) { > + return false; > + } > + > + /* > + * With VMSA, if translation is disabled, then the default memory type > + * is Device(-nGnRnE) instead of Normal, which requires that alignment > * be enforced. Since this affects all ram, it is most efficient > * to handle this during translation. > */ This one is in target-arm.next: https://lore.kernel.org/qemu-devel/CAFEAcA98UrBLsAXKzLSkUnC2G_RZd56veqUkSGSttoADfkEKGA@mail.gmail.com/