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Wed, 16 Apr 2025 11:58:02 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c33ef0f2bsm18098825ad.27.2025.04.16.11.58.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Apr 2025 11:58:02 -0700 (PDT) Message-ID: <490d761b-4658-45e7-81bc-b1cfa7bd32f2@linaro.org> Date: Wed, 16 Apr 2025 11:58:01 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 120/163] tcg/i386: Implement add/sub carry opcodes Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-121-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250415192515.232910-121-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/25 12:24, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target.c.inc | 86 ++++++++++++++++++++++++++++++++------- > 1 file changed, 72 insertions(+), 14 deletions(-) > > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 8e0ccbc722..52d3402f29 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -424,6 +424,7 @@ static bool tcg_target_const_match(int64_t val, int ct, > #define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) > #define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) > #define OPC_SHRD_Ib (0xac | P_EXT) > +#define OPC_STC (0xf9) > #define OPC_TESTB (0x84) > #define OPC_TESTL (0x85) > #define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) > @@ -2629,21 +2630,55 @@ static const TCGOutOpBinary outop_add = { > .out_rri = tgen_addi, > }; > > +static void tgen_addco(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, TCGReg a2) > +{ > + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > + tgen_arithr(s, ARITH_ADD + rexw, a0, a2); > +} > + > +static void tgen_addco_imm(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, tcg_target_long a2) > +{ > + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > + tgen_arithi(s, ARITH_ADD + rexw, a0, a2, true); > +} > + > static const TCGOutOpBinary outop_addco = { > - .base.static_constraint = C_NotImplemented, > + .base.static_constraint = C_O1_I2(r, 0, re), > + .out_rrr = tgen_addco, > + .out_rri = tgen_addco_imm, > +}; > + > +static void tgen_addcio(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, TCGReg a2) > +{ > + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > + tgen_arithr(s, ARITH_ADC + rexw, a0, a2); > +} > + > +static void tgen_addcio_imm(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, tcg_target_long a2) > +{ > + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > + tgen_arithi(s, ARITH_ADC + rexw, a0, a2, true); > +} > + > +static const TCGOutOpBinary outop_addcio = { > + .base.static_constraint = C_O1_I2(r, 0, re), > + .out_rrr = tgen_addcio, > + .out_rri = tgen_addcio_imm, > }; > > static const TCGOutOpAddSubCarry outop_addci = { > - .base.static_constraint = C_NotImplemented, > -}; > - > -static const TCGOutOpBinary outop_addcio = { > - .base.static_constraint = C_NotImplemented, > + .base.static_constraint = C_O1_I2(r, 0, re), > + .out_rrr = tgen_addcio, > + .out_rri = tgen_addcio_imm, > }; > > static void tcg_out_set_carry(TCGContext *s) > { > - g_assert_not_reached(); > + tcg_out8(s, OPC_STC); > } > > static void tgen_and(TCGContext *s, TCGType type, > @@ -3060,7 +3095,7 @@ static const TCGOutOpBinary outop_shr = { > }; > > static void tgen_sub(TCGContext *s, TCGType type, > - TCGReg a0, TCGReg a1, TCGReg a2) > + TCGReg a0, TCGReg a1, TCGReg a2) > { > int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > tgen_arithr(s, ARITH_SUB + rexw, a0, a2); > @@ -3071,21 +3106,44 @@ static const TCGOutOpSubtract outop_sub = { > .out_rrr = tgen_sub, > }; > > +static void tgen_subbo_rri(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, tcg_target_long a2) > +{ > + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > + tgen_arithi(s, ARITH_SUB + rexw, a0, a2, 1); > +} > + > static const TCGOutOpAddSubCarry outop_subbo = { > - .base.static_constraint = C_NotImplemented, > + .base.static_constraint = C_O1_I2(r, 0, re), > + .out_rrr = tgen_sub, > + .out_rri = tgen_subbo_rri, > }; > > -static const TCGOutOpAddSubCarry outop_subbi = { > - .base.static_constraint = C_NotImplemented, > -}; > +static void tgen_subbio_rrr(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, TCGReg a2) > +{ > + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > + tgen_arithr(s, ARITH_SBB + rexw, a0, a2); > +} > + > +static void tgen_subbio_rri(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, tcg_target_long a2) > +{ > + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > + tgen_arithi(s, ARITH_SBB + rexw, a0, a2, 1); > +} > > static const TCGOutOpAddSubCarry outop_subbio = { > - .base.static_constraint = C_NotImplemented, > + .base.static_constraint = C_O1_I2(r, 0, re), > + .out_rrr = tgen_subbio_rrr, > + .out_rri = tgen_subbio_rri, > }; > > +#define outop_subbi outop_subbio > + > static void tcg_out_set_borrow(TCGContext *s) > { > - g_assert_not_reached(); > + tcg_out8(s, OPC_STC); > } > > static void tgen_xor(TCGContext *s, TCGType type, Reviewed-by: Pierrick Bouvier