* [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4
@ 2008-11-02 2:12 Shin-ichiro KAWASAKI
2008-11-02 3:27 ` andrzej zaborowski
2008-11-02 6:52 ` Blue Swirl
0 siblings, 2 replies; 14+ messages in thread
From: Shin-ichiro KAWASAKI @ 2008-11-02 2:12 UTC (permalink / raw)
To: qemu-devel
Hi, all!
This patch adds minimum emulation of SM501 multifunction device,
whose main feature is 2D graphics. It is one of the peripheral
of R2D, the SH4 evaluation board. We can see TUX printed on the
QEMU console.
Review on the patch and merging it to the trunk will be appreciated.
I'm not sure about following two points.
- Register definitions were copied from Linux : include/linux/sm501-regs.h
- Function prototype is put into "into hw/devices.h". Is it right place?
Regards,
Shin-ichiro KAWASAKI
Signed-off-by: Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp>
Index: trunk/Makefile.target
===================================================================
--- trunk/Makefile.target (revision 5594)
+++ trunk/Makefile.target (working copy)
@@ -725,7 +725,7 @@
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
-OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o
+OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o
endif
ifeq ($(TARGET_BASE_ARCH), m68k)
OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
Index: trunk/hw/r2d.c
===================================================================
--- trunk/hw/r2d.c (revision 5594)
+++ trunk/hw/r2d.c (working copy)
@@ -25,6 +25,7 @@
#include "hw.h"
#include "sh.h"
+#include "devices.h"
#include "sysemu.h"
#include "boards.h"
@@ -148,6 +149,7 @@
/* Register peripherals */
r2d_fpga_init(0x04000000);
s = sh7750_init(env);
+ sm501_init(ds, 0x10000000, (8*1024*1024));
/* Todo: register on board registers */
{
int kernel_size;
Index: trunk/hw/sm501.c
===================================================================
--- trunk/hw/sm501.c (revision 0)
+++ trunk/hw/sm501.c (revision 0)
@@ -0,0 +1,702 @@
+/*
+ * QEMU SM501 Device
+ *
+ * Copyright (c) 2008 Shin-ichiro KAWASAKI
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <assert.h>
+#include "hw.h"
+#include "console.h"
+#include "vga_int.h"
+#include "sm501-regs.h"
+
+/*
+ * Status: 2008/11/02
+ * - Minimum implementation for Linux console : mmio regs and CRT layer.
+ * - Always updates full screen.
+ *
+ * TODO:
+ * - Panel support
+ * - Hardware cursor support
+ * - Touch panel support
+ * - USB support
+ * - UART support
+ * - Performance tuning
+ */
+
+//#define DEBUG_SM501
+//#define DEBUG_BITBLT
+
+#ifdef DEBUG_SM501
+#define SM501_DPRINTF(fmt...) printf(fmt)
+#else
+#define SM501_DPRINTF(fmt...) do {} while(0)
+#endif
+
+
+#define MMIO_BASE_OFFSET 0x3e00000
+
+#define UART_RX_OFFSET 0x00
+#define UART_TX_OFFSET 0x00
+#define UART_IER_OFFSET 0x04
+#define UART_IIR_OFFSET 0x08
+#define UART_FCR_OFFSET 0x08
+#define UART_LCR_OFFSET 0x0C
+#define UART_MCR_OFFSET 0x10
+#define UART_LSR_OFFSET 0x14
+#define UART_MSR_OFFSET 0x18
+#define UART_SCR_OFFSET 0x1C
+
+/* taken from "linux/drivers/mfd/sm501.c" */
+static uint32_t sm501_mem_local_size[] = {
+ [0] = 4*1024*1024,
+ [1] = 8*1024*1024,
+ [2] = 16*1024*1024,
+ [3] = 32*1024*1024,
+ [4] = 64*1024*1024,
+ [5] = 2*1024*1024,
+};
+#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
+
+typedef struct SM501State {
+ /* graphic console status */
+ DisplayState *ds;
+ QEMUConsole *console;
+
+ /* status & internal resources */
+ target_phys_addr_t base;
+ uint32_t local_mem_size_index;
+ uint8_t * local_mem;
+ uint32_t last_width;
+ uint32_t last_height;
+
+ /* mmio registers */
+ uint32_t system_control;
+ uint32_t misc_control;
+ uint32_t gpio_31_0_control;
+ uint32_t gpio_63_32_control;
+ uint32_t dram_control;
+ uint32_t irq_mask;
+ uint32_t misc_timing;
+ uint32_t power_mode_control;
+
+ uint32_t uart0_ier;
+ uint32_t uart0_lcr;
+ uint32_t uart0_mcr;
+ uint32_t uart0_scr;
+
+ uint8_t dc_panel_palette[0x400];
+ uint8_t dc_video_palette[0x400];
+ uint8_t dc_crt_palette[0x400];
+
+ uint32_t dc_panel_control;
+ uint32_t dc_panel_panning_control;
+ uint32_t dc_panel_fb_addr;
+ uint32_t dc_panel_fb_offset;
+ uint32_t dc_panel_fb_width;
+ uint32_t dc_panel_fb_height;
+ uint32_t dc_panel_tl_location;
+ uint32_t dc_panel_br_location;
+ uint32_t dc_panel_h_total;
+ uint32_t dc_panel_h_sync;
+ uint32_t dc_panel_v_total;
+ uint32_t dc_panel_v_sync;
+
+ uint32_t dc_panel_hwc_addr;
+ uint32_t dc_panel_hwc_location;
+ uint32_t dc_panel_hwc_color_1_2;
+ uint32_t dc_panel_hwc_color_3;
+
+ uint32_t dc_crt_control;
+ uint32_t dc_crt_fb_addr;
+ uint32_t dc_crt_fb_offset;
+ uint32_t dc_crt_h_total;
+ uint32_t dc_crt_h_sync;
+ uint32_t dc_crt_v_total;
+ uint32_t dc_crt_v_sync;
+
+ uint32_t dc_crt_hwc_addr;
+ uint32_t dc_crt_hwc_location;
+ uint32_t dc_crt_hwc_color_1_2;
+ uint32_t dc_crt_hwc_color_3;
+
+} SM501State;
+
+static uint32_t get_local_mem_size_index(uint32_t size)
+{
+ uint32_t norm_size = 0;
+ int i, index = 0;
+
+ for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) {
+ uint32_t new_size = sm501_mem_local_size[i];
+ if (new_size >= size) {
+ if (norm_size == 0 || norm_size > new_size) {
+ norm_size = new_size;
+ index = i;
+ }
+ }
+ }
+
+ return index;
+}
+
+static uint32_t sm501_mmio_read(void *opaque, target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
+ uint32_t ret = 0;
+ SM501_DPRINTF("sm501 read addr=%x, offset=%x\n", addr, offset);
+
+ if (SM501_DC + SM501_DC_PANEL_PALETTE <= offset
+ && offset < SM501_DC + SM501_DC_VIDEO_PALETTE) {
+ offset -= SM501_DC + SM501_DC_PANEL_PALETTE;
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+ ret = *(uint32_t*)&s->dc_panel_palette[offset];
+ } else if (SM501_DC + SM501_DC_VIDEO_PALETTE <= offset
+ && offset < SM501_DC + SM501_DC_CRT_PALETTE) {
+ offset -= SM501_DC + SM501_DC_VIDEO_PALETTE;
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+ ret = *(uint32_t*)&s->dc_video_palette[offset];
+ } else if (SM501_DC + SM501_DC_CRT_PALETTE <= offset
+ && offset < SM501_DC + SM501_DC_CRT_PALETTE + 0x400) {
+ offset -= SM501_DC + SM501_DC_CRT_PALETTE;
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+ ret = *(uint32_t*)&s->dc_crt_palette[offset];
+ } else {
+ switch(offset) {
+ case SM501_SYSTEM_CONTROL:
+ ret = s->system_control;
+ break;
+ case SM501_MISC_CONTROL:
+ ret = s->misc_control;
+ break;
+ case SM501_GPIO31_0_CONTROL:
+ ret = s->gpio_31_0_control;
+ break;
+ case SM501_GPIO63_32_CONTROL:
+ ret = s->gpio_63_32_control;
+ break;
+ case SM501_DEVICEID:
+ ret = 0x050100A0;
+ break;
+ case SM501_DRAM_CONTROL:
+ ret = (s->dram_control & 0x07F107C0)
+ | s->local_mem_size_index << 13;
+ break;
+ case SM501_IRQ_MASK:
+ ret = s->irq_mask;
+ break;
+ case SM501_MISC_TIMING:
+ /* TODO : simulate gate control */
+ ret = s->misc_timing;
+ break;
+ case SM501_CURRENT_GATE:
+ /* TODO : simulate gate control */
+ ret = 0x00021807;
+ break;
+ case SM501_CURRENT_CLOCK:
+ ret = 0x2A1A0A09;
+ break;
+ case SM501_POWER_MODE_CONTROL:
+ ret = s->power_mode_control;
+ break;
+
+ /* TODO : implement SM501 UART */
+ case SM501_UART0 + UART_RX_OFFSET:
+ ret = 0;
+ break;
+ case SM501_UART0 + UART_IER_OFFSET:
+ ret = s->uart0_ier;
+ break;
+ case SM501_UART0 + UART_IIR_OFFSET:
+ ret = 0x01;
+ break;
+ case SM501_UART0 + UART_LCR_OFFSET:
+ ret = s->uart0_lcr;
+ break;
+ case SM501_UART0 + UART_MCR_OFFSET:
+ ret = s->uart0_mcr;
+ break;
+ case SM501_UART0 + UART_SCR_OFFSET:
+ ret = s->uart0_scr;
+ break;
+
+ case SM501_DC + SM501_DC_PANEL_CONTROL:
+ ret = s->dc_panel_control;
+ break;
+ case SM501_DC + SM501_DC_PANEL_PANNING_CONTROL:
+ ret = s->dc_panel_panning_control;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_ADDR:
+ ret = s->dc_panel_fb_addr;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_OFFSET:
+ ret = s->dc_panel_fb_offset;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_WIDTH:
+ ret = s->dc_panel_fb_width;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_HEIGHT:
+ ret = s->dc_panel_fb_height;
+ break;
+ case SM501_DC + SM501_DC_PANEL_TL_LOC:
+ ret = s->dc_panel_tl_location;
+ break;
+ case SM501_DC + SM501_DC_PANEL_BR_LOC:
+ ret = s->dc_panel_br_location;
+ break;
+
+ case SM501_DC + SM501_DC_PANEL_H_TOT:
+ ret = s->dc_panel_h_total;
+ break;
+ case SM501_DC + SM501_DC_PANEL_H_SYNC:
+ ret = s->dc_panel_h_sync;
+ break;
+ case SM501_DC + SM501_DC_PANEL_V_TOT:
+ ret = s->dc_panel_v_total;
+ break;
+ case SM501_DC + SM501_DC_PANEL_V_SYNC:
+ ret = s->dc_panel_v_sync;
+ break;
+
+ case SM501_DC + SM501_DC_CRT_CONTROL:
+ ret = s->dc_crt_control;
+ break;
+ case SM501_DC + SM501_DC_CRT_FB_ADDR:
+ ret = s->dc_crt_fb_addr;
+ break;
+ case SM501_DC + SM501_DC_CRT_FB_OFFSET:
+ ret = s->dc_crt_fb_offset;
+ break;
+ case SM501_DC + SM501_DC_CRT_H_TOT:
+ ret = s->dc_crt_h_total;
+ break;
+ case SM501_DC + SM501_DC_CRT_H_SYNC:
+ ret = s->dc_crt_h_sync;
+ break;
+ case SM501_DC + SM501_DC_CRT_V_TOT:
+ ret = s->dc_crt_v_total;
+ break;
+ case SM501_DC + SM501_DC_CRT_V_SYNC:
+ ret = s->dc_crt_v_sync;
+ break;
+
+ case SM501_DC + SM501_DC_CRT_HWC_ADDR:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC + SM501_DC_CRT_HWC_LOC:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC + SM501_DC_CRT_HWC_COLOR_1_2:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC + SM501_DC_CRT_HWC_COLOR_3:
+ ret = s->dc_crt_hwc_addr;
+ break;
+
+ default:
+ printf("sm501 not implement read addr=%x, offset=%x\n",
+ addr, offset);
+ assert(0);
+ }
+ }
+ return ret;
+}
+
+static uint32_t sm501_mmio_readb(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_mmio_read(opaque, addr);
+}
+
+static uint32_t sm501_mmio_readw(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_mmio_read(opaque, addr);
+}
+
+static uint32_t sm501_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_mmio_read(opaque, addr);
+}
+
+static void sm501_mmio_write(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
+ SM501_DPRINTF("sm501 write addr=%x, ofs=%x, val=%x\n",
+ addr, offset, value);
+
+ if (SM501_DC + SM501_DC_PANEL_PALETTE <= offset
+ && offset < SM501_DC + SM501_DC_VIDEO_PALETTE) {
+ offset -= SM501_DC + SM501_DC_PANEL_PALETTE;
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+ *(uint32_t*)&s->dc_panel_palette[offset] = value;
+ } else if (SM501_DC + SM501_DC_VIDEO_PALETTE <= offset
+ && offset < SM501_DC + SM501_DC_CRT_PALETTE) {
+ offset -= SM501_DC + SM501_DC_VIDEO_PALETTE;
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+ *(uint32_t*)&s->dc_video_palette[offset] = value;
+ } else if (SM501_DC + SM501_DC_CRT_PALETTE <= offset
+ && offset < SM501_DC + SM501_DC_CRT_PALETTE + 0x400) {
+ offset -= SM501_DC + SM501_DC_CRT_PALETTE;
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+ *(uint32_t*)&s->dc_crt_palette[offset] = value;
+ } else {
+ switch(offset) {
+ case SM501_SYSTEM_CONTROL:
+ s->system_control = value & 0xE300B8F7;
+ break;
+ case SM501_MISC_CONTROL:
+ s->misc_control = value & 0xFF7FFF20;
+ break;
+ case SM501_GPIO31_0_CONTROL:
+ s->gpio_31_0_control = value;
+ break;
+ case SM501_GPIO63_32_CONTROL:
+ s->gpio_63_32_control = value;
+ break;
+ case SM501_DRAM_CONTROL:
+ s->local_mem_size_index = (value >> 13) & 0x7;
+ /* TODO : check validity of size change */
+ s->dram_control |= value & 0x7FFFFFC3;
+ break;
+ case SM501_IRQ_MASK:
+ s->irq_mask = value;
+ break;
+ case SM501_MISC_TIMING:
+ s->misc_timing = value & 0xF31F1FFF;
+ break;
+ case SM501_POWER_MODE_0_GATE:
+ case SM501_POWER_MODE_1_GATE:
+ case SM501_POWER_MODE_0_CLOCK:
+ case SM501_POWER_MODE_1_CLOCK:
+ /* TODO : simulate gate & clock control */
+ break;
+ case SM501_POWER_MODE_CONTROL:
+ s->power_mode_control = value & 0x00000003;
+ break;
+
+ /* TODO : implement SM501 UART */
+ case SM501_UART0 + UART_IER_OFFSET:
+ s->uart0_ier = value & 0xef;
+ break;
+ case SM501_UART0 + UART_FCR_OFFSET:
+ /* throw it away */
+ break;
+ case SM501_UART0 + UART_LCR_OFFSET:
+ s->uart0_lcr = value & 0xff;
+ break;
+ case SM501_UART0 + UART_MCR_OFFSET:
+ s->uart0_mcr = value & 0x5f;
+ break;
+ case SM501_UART0 + UART_SCR_OFFSET:
+ s->uart0_scr = value & 0xff;
+ break;
+
+ case SM501_DC + SM501_DC_PANEL_CONTROL:
+ s->dc_panel_control = value & 0x0FFF73FF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_PANNING_CONTROL:
+ s->dc_panel_panning_control = value & 0xFF3FFF3F;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_ADDR:
+ s->dc_panel_fb_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_OFFSET:
+ s->dc_panel_fb_offset = value & 0x3FF03FF0;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_WIDTH:
+ s->dc_panel_fb_width = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_FB_HEIGHT:
+ s->dc_panel_fb_height = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_TL_LOC:
+ s->dc_panel_tl_location = value & 0x07FF07FF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_BR_LOC:
+ s->dc_panel_br_location = value & 0x07FF07FF;
+ break;
+
+ case SM501_DC + SM501_DC_PANEL_H_TOT:
+ s->dc_panel_h_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_H_SYNC:
+ s->dc_panel_h_sync = value & 0x00FF0FFF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_V_TOT:
+ s->dc_panel_v_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_V_SYNC:
+ s->dc_panel_v_sync = value & 0x003F0FFF;
+ break;
+
+ case SM501_DC + SM501_DC_PANEL_HWC_ADDR:
+ s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC + SM501_DC_PANEL_HWC_LOC:
+ s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_PANEL_HWC_COLOR_1_2:
+ s->dc_panel_hwc_addr = value;
+ break;
+ case SM501_DC + SM501_DC_PANEL_HWC_COLOR_3:
+ s->dc_panel_hwc_addr = value & 0x0000FFFF;
+ break;
+
+ case SM501_DC + SM501_DC_CRT_CONTROL:
+ s->dc_crt_control = value & 0x0003FFFF;
+ break;
+ case SM501_DC + SM501_DC_CRT_FB_ADDR:
+ s->dc_crt_fb_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC + SM501_DC_CRT_FB_OFFSET:
+ s->dc_crt_fb_offset = value & 0x3FF03FF0;
+ break;
+ case SM501_DC + SM501_DC_CRT_H_TOT:
+ s->dc_crt_h_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_CRT_H_SYNC:
+ s->dc_crt_h_sync = value & 0x00FF0FFF;
+ break;
+ case SM501_DC + SM501_DC_CRT_V_TOT:
+ s->dc_crt_v_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_CRT_V_SYNC:
+ s->dc_crt_v_sync = value & 0x003F0FFF;
+ break;
+
+ case SM501_DC + SM501_DC_CRT_HWC_ADDR:
+ s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC + SM501_DC_CRT_HWC_LOC:
+ s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC + SM501_DC_CRT_HWC_COLOR_1_2:
+ s->dc_crt_hwc_addr = value;
+ break;
+ case SM501_DC + SM501_DC_CRT_HWC_COLOR_3:
+ s->dc_crt_hwc_addr = value & 0x0000FFFF;
+ break;
+
+ default:
+ printf("sm501 not implement write addr=%x, val=%x\n",
+ addr, value);
+ assert(0);
+ }
+ }
+}
+
+static void sm501_mmio_writeb(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_mmio_write(opaque, addr, value);
+}
+
+static void sm501_mmio_writew(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_mmio_write(opaque, addr, value);
+}
+
+static void sm501_mmio_writel(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_mmio_write(opaque, addr, value);
+}
+
+static CPUReadMemoryFunc *sm501_mmio_readfn[] = {
+ &sm501_mmio_readb,
+ &sm501_mmio_readw,
+ &sm501_mmio_readl,
+};
+
+static CPUWriteMemoryFunc *sm501_mmio_writefn[] = {
+ &sm501_mmio_writeb,
+ &sm501_mmio_writew,
+ &sm501_mmio_writel,
+};
+
+static uint32_t sm501_lm_read(void *opaque, target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - s->base;
+ return *(uint32_t*)&s->local_mem[offset];
+}
+
+static uint32_t sm501_lm_readb(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_lm_read(opaque, addr);
+}
+
+static uint32_t sm501_lm_readw(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_lm_read(opaque, addr);
+}
+
+static uint32_t sm501_lm_readl(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_lm_read(opaque, addr);
+}
+
+static void sm501_lm_write(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - s->base;
+ *(uint32_t*)&s->local_mem[offset] = value;
+}
+
+static void sm501_lm_writeb(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_lm_write(opaque, addr, value);
+}
+
+static void sm501_lm_writew(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_lm_write(opaque, addr, value);
+}
+
+static void sm501_lm_writel(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_lm_write(opaque, addr, value);
+}
+
+static CPUReadMemoryFunc *sm501_lm_readfn[] = {
+ &sm501_lm_readb,
+ &sm501_lm_readw,
+ &sm501_lm_readl,
+};
+
+static CPUWriteMemoryFunc *sm501_lm_writefn[] = {
+ &sm501_lm_writeb,
+ &sm501_lm_writew,
+ &sm501_lm_writel,
+};
+
+static void sm501_draw_crt(SM501State * s)
+{
+ int x, y;
+ uint32_t crt_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
+ uint32_t crt_height = (s->dc_crt_v_total & 0x00000FFF) + 1;
+ uint8_t * buf = s->local_mem;
+ uint32_t * palette = (uint32_t *)s->dc_crt_palette;
+
+ /* adjust console size */
+ if (s->last_width != crt_width || s->last_height != crt_height) {
+ qemu_console_resize(s->console, crt_width, crt_height);
+ s->last_width = crt_width;
+ s->last_height = crt_height;
+ }
+
+ switch (s->dc_crt_control & 3) {
+ case SM501_DC_CRT_CONTROL_8BPP:
+ for (y = 0; y < crt_height; y++) {
+ for (x = 0; x < crt_width; x++) {
+ int i = (y * crt_width + x) * 4;
+ *(uint32_t *)&s->ds->data[i] = palette[*buf];
+ buf++;
+ }
+ }
+ break;
+ case SM501_DC_CRT_CONTROL_16BPP:
+ for (y = 0; y < crt_height; y++) {
+ for (x = 0; x < crt_width; x++) {
+ int i = (y * crt_width + x) * 4;
+ uint32_t rgb565 = *(uint16_t*)buf;
+ int r = ((rgb565 >> 11) & 0x1f) << 3;
+ int g = ((rgb565 >> 5) & 0x3f) << 2;
+ int b = ((rgb565 >> 0) & 0x1f) << 3;
+ s->ds->data[i + 0] = b;
+ s->ds->data[i + 1] = g;
+ s->ds->data[i + 2] = r;
+ s->ds->data[i + 3] = 0;
+ buf += 2;
+ }
+ }
+ break;
+ case SM501_DC_CRT_CONTROL_32BPP:
+ for (y = 0; y < crt_height; y++) {
+ for (x = 0; x < crt_width; x++) {
+ int i = (y * crt_width + x) * 4;
+ *(uint32_t *)&s->ds->data[i] = *(uint32_t*)buf;
+ buf += 4;
+ }
+ }
+ break;
+ }
+
+ dpy_update(s->ds, 0, 0, crt_width, crt_height);
+
+}
+
+static void sm501_update_display(void *opaque)
+{
+ SM501State * s = (SM501State *)opaque;
+
+ if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
+ sm501_draw_crt(s);
+}
+
+void sm501_init(DisplayState *ds, uint32_t base, uint32_t local_mem_bytes)
+{
+ SM501State * s;
+ int sm501_mmio_index, sm501_lm_index;
+
+ /* allocate management data region */
+ s = (SM501State *)qemu_mallocz(sizeof(SM501State));
+ s->base = base;
+ s->local_mem_size_index
+ = get_local_mem_size_index(local_mem_bytes);
+ SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
+ s->local_mem_size_index);
+ s->system_control = 0x00100000;
+ s->misc_control = 0x00001000; /* assumes SH, active=low */
+ s->dc_panel_control = 0x00010000;
+ s->dc_crt_control = 0x00010000;
+ s->ds = ds;
+
+ /* allocate local memory */
+ s->local_mem = qemu_mallocz(get_local_mem_size(s));
+ sm501_lm_index = cpu_register_io_memory(0, sm501_lm_readfn,
+ sm501_lm_writefn, s);
+ cpu_register_physical_memory(base, get_local_mem_size(s), sm501_lm_index);
+
+ /* map mmio */
+ sm501_mmio_index = cpu_register_io_memory(0, sm501_mmio_readfn,
+ sm501_mmio_writefn, s);
+ cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
+ 0x150000, sm501_mmio_index);
+
+ /* create qemu graphic console */
+ s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
+ NULL, NULL, s);
+}
Index: trunk/hw/sm501-regs.h
===================================================================
--- trunk/hw/sm501-regs.h (revision 0)
+++ trunk/hw/sm501-regs.h (revision 0)
@@ -0,0 +1,386 @@
+/* sm501-regs.h
+ *
+ * Copyright 2006 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Silicon Motion SM501 register definitions
+*/
+
+/* System Configuration area */
+/* System config base */
+#define SM501_SYS_CONFIG (0x000000)
+
+/* config 1 */
+#define SM501_SYSTEM_CONTROL (0x000000)
+
+#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
+#define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
+#define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
+
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
+
+#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
+#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
+#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
+#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
+
+/* miscellaneous control */
+
+#define SM501_MISC_CONTROL (0x000004)
+
+#define SM501_MISC_BUS_SH (0x0)
+#define SM501_MISC_BUS_PCI (0x1)
+#define SM501_MISC_BUS_XSCALE (0x2)
+#define SM501_MISC_BUS_NEC (0x6)
+#define SM501_MISC_BUS_MASK (0x7)
+
+#define SM501_MISC_VR_62MB (1<<3)
+#define SM501_MISC_CDR_RESET (1<<7)
+#define SM501_MISC_USB_LB (1<<8)
+#define SM501_MISC_USB_SLAVE (1<<9)
+#define SM501_MISC_BL_1 (1<<10)
+#define SM501_MISC_MC (1<<11)
+#define SM501_MISC_DAC_POWER (1<<12)
+#define SM501_MISC_IRQ_INVERT (1<<16)
+#define SM501_MISC_SH (1<<17)
+
+#define SM501_MISC_HOLD_EMPTY (0<<18)
+#define SM501_MISC_HOLD_8 (1<<18)
+#define SM501_MISC_HOLD_16 (2<<18)
+#define SM501_MISC_HOLD_24 (3<<18)
+#define SM501_MISC_HOLD_32 (4<<18)
+#define SM501_MISC_HOLD_MASK (7<<18)
+
+#define SM501_MISC_FREQ_12 (1<<24)
+#define SM501_MISC_PNL_24BIT (1<<25)
+#define SM501_MISC_8051_LE (1<<26)
+
+
+
+#define SM501_GPIO31_0_CONTROL (0x000008)
+#define SM501_GPIO63_32_CONTROL (0x00000C)
+#define SM501_DRAM_CONTROL (0x000010)
+
+/* command list */
+#define SM501_ARBTRTN_CONTROL (0x000014)
+
+/* command list */
+#define SM501_COMMAND_LIST_STATUS (0x000024)
+
+/* interrupt debug */
+#define SM501_RAW_IRQ_STATUS (0x000028)
+#define SM501_RAW_IRQ_CLEAR (0x000028)
+#define SM501_IRQ_STATUS (0x00002C)
+#define SM501_IRQ_MASK (0x000030)
+#define SM501_DEBUG_CONTROL (0x000034)
+
+/* power management */
+#define SM501_POWERMODE_P2X_SRC (1<<29)
+#define SM501_POWERMODE_V2X_SRC (1<<20)
+#define SM501_POWERMODE_M_SRC (1<<12)
+#define SM501_POWERMODE_M1_SRC (1<<4)
+
+#define SM501_CURRENT_GATE (0x000038)
+#define SM501_CURRENT_CLOCK (0x00003C)
+#define SM501_POWER_MODE_0_GATE (0x000040)
+#define SM501_POWER_MODE_0_CLOCK (0x000044)
+#define SM501_POWER_MODE_1_GATE (0x000048)
+#define SM501_POWER_MODE_1_CLOCK (0x00004C)
+#define SM501_SLEEP_MODE_GATE (0x000050)
+#define SM501_POWER_MODE_CONTROL (0x000054)
+
+/* power gates for units within the 501 */
+#define SM501_GATE_HOST (0)
+#define SM501_GATE_MEMORY (1)
+#define SM501_GATE_DISPLAY (2)
+#define SM501_GATE_2D_ENGINE (3)
+#define SM501_GATE_CSC (4)
+#define SM501_GATE_ZVPORT (5)
+#define SM501_GATE_GPIO (6)
+#define SM501_GATE_UART0 (7)
+#define SM501_GATE_UART1 (8)
+#define SM501_GATE_SSP (10)
+#define SM501_GATE_USB_HOST (11)
+#define SM501_GATE_USB_GADGET (12)
+#define SM501_GATE_UCONTROLLER (17)
+#define SM501_GATE_AC97 (18)
+
+/* panel clock */
+#define SM501_CLOCK_P2XCLK (24)
+/* crt clock */
+#define SM501_CLOCK_V2XCLK (16)
+/* main clock */
+#define SM501_CLOCK_MCLK (8)
+/* SDRAM controller clock */
+#define SM501_CLOCK_M1XCLK (0)
+
+/* config 2 */
+#define SM501_PCI_MASTER_BASE (0x000058)
+#define SM501_ENDIAN_CONTROL (0x00005C)
+#define SM501_DEVICEID (0x000060)
+/* 0x050100A0 */
+
+#define SM501_DEVICEID_SM501 (0x05010000)
+#define SM501_DEVICEID_IDMASK (0xffff0000)
+#define SM501_DEVICEID_REVMASK (0x000000ff)
+
+#define SM501_PLLCLOCK_COUNT (0x000064)
+#define SM501_MISC_TIMING (0x000068)
+#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
+
+#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
+
+/* GPIO base */
+#define SM501_GPIO (0x010000)
+#define SM501_GPIO_DATA_LOW (0x00)
+#define SM501_GPIO_DATA_HIGH (0x04)
+#define SM501_GPIO_DDR_LOW (0x08)
+#define SM501_GPIO_DDR_HIGH (0x0C)
+#define SM501_GPIO_IRQ_SETUP (0x10)
+#define SM501_GPIO_IRQ_STATUS (0x14)
+#define SM501_GPIO_IRQ_RESET (0x14)
+
+/* I2C controller base */
+#define SM501_I2C (0x010040)
+#define SM501_I2C_BYTE_COUNT (0x00)
+#define SM501_I2C_CONTROL (0x01)
+#define SM501_I2C_STATUS (0x02)
+#define SM501_I2C_RESET (0x02)
+#define SM501_I2C_SLAVE_ADDRESS (0x03)
+#define SM501_I2C_DATA (0x04)
+
+/* SSP base */
+#define SM501_SSP (0x020000)
+
+/* Uart 0 base */
+#define SM501_UART0 (0x030000)
+
+/* Uart 1 base */
+#define SM501_UART1 (0x030020)
+
+/* USB host port base */
+#define SM501_USB_HOST (0x040000)
+
+/* USB slave/gadget base */
+#define SM501_USB_GADGET (0x060000)
+
+/* USB slave/gadget data port base */
+#define SM501_USB_GADGET_DATA (0x070000)
+
+/* Display controller/video engine base */
+#define SM501_DC (0x080000)
+
+/* common defines for the SM501 address registers */
+#define SM501_ADDR_FLIP (1<<31)
+#define SM501_ADDR_EXT (1<<27)
+#define SM501_ADDR_CS1 (1<<26)
+#define SM501_ADDR_MASK (0x3f << 26)
+
+#define SM501_FIFO_MASK (0x3 << 16)
+#define SM501_FIFO_1 (0x0 << 16)
+#define SM501_FIFO_3 (0x1 << 16)
+#define SM501_FIFO_7 (0x2 << 16)
+#define SM501_FIFO_11 (0x3 << 16)
+
+/* common registers for panel and the crt */
+#define SM501_OFF_DC_H_TOT (0x000)
+#define SM501_OFF_DC_V_TOT (0x008)
+#define SM501_OFF_DC_H_SYNC (0x004)
+#define SM501_OFF_DC_V_SYNC (0x00C)
+
+#define SM501_DC_PANEL_CONTROL (0x000)
+
+#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
+#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
+#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
+#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
+#define SM501_DC_PANEL_CONTROL_DP (1<<23)
+
+#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
+
+#define SM501_DC_PANEL_CONTROL_DE (1<<20)
+
+#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
+
+#define SM501_DC_PANEL_CONTROL_CP (1<<14)
+#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
+#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
+#define SM501_DC_PANEL_CONTROL_CK (1<<9)
+#define SM501_DC_PANEL_CONTROL_TE (1<<8)
+#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
+#define SM501_DC_PANEL_CONTROL_VP (1<<6)
+#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
+#define SM501_DC_PANEL_CONTROL_HP (1<<4)
+#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
+#define SM501_DC_PANEL_CONTROL_EN (1<<2)
+
+#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
+#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
+#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
+
+
+#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
+#define SM501_DC_PANEL_COLOR_KEY (0x008)
+#define SM501_DC_PANEL_FB_ADDR (0x00C)
+#define SM501_DC_PANEL_FB_OFFSET (0x010)
+#define SM501_DC_PANEL_FB_WIDTH (0x014)
+#define SM501_DC_PANEL_FB_HEIGHT (0x018)
+#define SM501_DC_PANEL_TL_LOC (0x01C)
+#define SM501_DC_PANEL_BR_LOC (0x020)
+#define SM501_DC_PANEL_H_TOT (0x024)
+#define SM501_DC_PANEL_H_SYNC (0x028)
+#define SM501_DC_PANEL_V_TOT (0x02C)
+#define SM501_DC_PANEL_V_SYNC (0x030)
+#define SM501_DC_PANEL_CUR_LINE (0x034)
+
+#define SM501_DC_VIDEO_CONTROL (0x040)
+#define SM501_DC_VIDEO_FB0_ADDR (0x044)
+#define SM501_DC_VIDEO_FB_WIDTH (0x048)
+#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
+#define SM501_DC_VIDEO_TL_LOC (0x050)
+#define SM501_DC_VIDEO_BR_LOC (0x054)
+#define SM501_DC_VIDEO_SCALE (0x058)
+#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
+#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
+#define SM501_DC_VIDEO_FB1_ADDR (0x064)
+#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
+
+#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
+#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
+#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
+#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
+#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
+#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
+#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
+#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
+#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
+#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
+
+#define SM501_DC_PANEL_HWC_BASE (0x0F0)
+#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
+#define SM501_DC_PANEL_HWC_LOC (0x0F4)
+#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
+#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
+
+#define SM501_HWC_EN (1<<31)
+
+#define SM501_OFF_HWC_ADDR (0x00)
+#define SM501_OFF_HWC_LOC (0x04)
+#define SM501_OFF_HWC_COLOR_1_2 (0x08)
+#define SM501_OFF_HWC_COLOR_3 (0x0C)
+
+#define SM501_DC_ALPHA_CONTROL (0x100)
+#define SM501_DC_ALPHA_FB_ADDR (0x104)
+#define SM501_DC_ALPHA_FB_OFFSET (0x108)
+#define SM501_DC_ALPHA_TL_LOC (0x10C)
+#define SM501_DC_ALPHA_BR_LOC (0x110)
+#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
+#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
+
+#define SM501_DC_CRT_CONTROL (0x200)
+
+#define SM501_DC_CRT_CONTROL_TVP (1<<15)
+#define SM501_DC_CRT_CONTROL_CP (1<<14)
+#define SM501_DC_CRT_CONTROL_VSP (1<<13)
+#define SM501_DC_CRT_CONTROL_HSP (1<<12)
+#define SM501_DC_CRT_CONTROL_VS (1<<11)
+#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
+#define SM501_DC_CRT_CONTROL_SEL (1<<9)
+#define SM501_DC_CRT_CONTROL_TE (1<<8)
+#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
+#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
+#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
+
+#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
+#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
+#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
+
+#define SM501_DC_CRT_FB_ADDR (0x204)
+#define SM501_DC_CRT_FB_OFFSET (0x208)
+#define SM501_DC_CRT_H_TOT (0x20C)
+#define SM501_DC_CRT_H_SYNC (0x210)
+#define SM501_DC_CRT_V_TOT (0x214)
+#define SM501_DC_CRT_V_SYNC (0x218)
+#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
+#define SM501_DC_CRT_CUR_LINE (0x220)
+#define SM501_DC_CRT_MONITOR_DETECT (0x224)
+
+#define SM501_DC_CRT_HWC_BASE (0x230)
+#define SM501_DC_CRT_HWC_ADDR (0x230)
+#define SM501_DC_CRT_HWC_LOC (0x234)
+#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
+#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
+
+#define SM501_DC_PANEL_PALETTE (0x400)
+
+#define SM501_DC_VIDEO_PALETTE (0x800)
+
+#define SM501_DC_CRT_PALETTE (0xC00)
+
+/* Zoom Video port base */
+#define SM501_ZVPORT (0x090000)
+
+/* AC97/I2S base */
+#define SM501_AC97 (0x0A0000)
+
+/* 8051 micro controller base */
+#define SM501_UCONTROLLER (0x0B0000)
+
+/* 8051 micro controller SRAM base */
+#define SM501_UCONTROLLER_SRAM (0x0C0000)
+
+/* DMA base */
+#define SM501_DMA (0x0D0000)
+
+/* 2d engine base */
+#define SM501_2D_ENGINE (0x100000)
+#define SM501_2D_SOURCE (0x00)
+#define SM501_2D_DESTINATION (0x04)
+#define SM501_2D_DIMENSION (0x08)
+#define SM501_2D_CONTROL (0x0C)
+#define SM501_2D_PITCH (0x10)
+#define SM501_2D_FOREGROUND (0x14)
+#define SM501_2D_BACKGROUND (0x18)
+#define SM501_2D_STRETCH (0x1C)
+#define SM501_2D_COLOR_COMPARE (0x20)
+#define SM501_2D_COLOR_COMPARE_MASK (0x24)
+#define SM501_2D_MASK (0x28)
+#define SM501_2D_CLIP_TL (0x2C)
+#define SM501_2D_CLIP_BR (0x30)
+#define SM501_2D_MONO_PATTERN_LOW (0x34)
+#define SM501_2D_MONO_PATTERN_HIGH (0x38)
+#define SM501_2D_WINDOW_WIDTH (0x3C)
+#define SM501_2D_SOURCE_BASE (0x40)
+#define SM501_2D_DESTINATION_BASE (0x44)
+#define SM501_2D_ALPHA (0x48)
+#define SM501_2D_WRAP (0x4C)
+#define SM501_2D_STATUS (0x50)
+
+#define SM501_CSC_Y_SOURCE_BASE (0xC8)
+#define SM501_CSC_CONSTANTS (0xCC)
+#define SM501_CSC_Y_SOURCE_X (0xD0)
+#define SM501_CSC_Y_SOURCE_Y (0xD4)
+#define SM501_CSC_U_SOURCE_BASE (0xD8)
+#define SM501_CSC_V_SOURCE_BASE (0xDC)
+#define SM501_CSC_SOURCE_DIMENSION (0xE0)
+#define SM501_CSC_SOURCE_PITCH (0xE4)
+#define SM501_CSC_DESTINATION (0xE8)
+#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
+#define SM501_CSC_DESTINATION_PITCH (0xF0)
+#define SM501_CSC_SCALE_FACTOR (0xF4)
+#define SM501_CSC_DESTINATION_BASE (0xF8)
+#define SM501_CSC_CONTROL (0xFC)
+
+/* 2d engine data port base */
+#define SM501_2D_ENGINE_DATA (0x110000)
Index: trunk/hw/devices.h
===================================================================
--- trunk/hw/devices.h (revision 5594)
+++ trunk/hw/devices.h (working copy)
@@ -71,4 +71,7 @@
qemu_irq handler);
qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
+/* sm501.c */
+void sm501_init(DisplayState *ds, uint32_t base, uint32_t local_mem_bytes);
+
#endif
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4
2008-11-02 2:12 [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4 Shin-ichiro KAWASAKI
@ 2008-11-02 3:27 ` andrzej zaborowski
2008-11-04 14:31 ` Shin-ichiro KAWASAKI
2008-11-02 6:52 ` Blue Swirl
1 sibling, 1 reply; 14+ messages in thread
From: andrzej zaborowski @ 2008-11-02 3:27 UTC (permalink / raw)
To: qemu-devel
Hi,
2008/11/2 Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp>:
> This patch adds minimum emulation of SM501 multifunction device,
> whose main feature is 2D graphics. It is one of the peripheral
> of R2D, the SH4 evaluation board. We can see TUX printed on the
> QEMU console.
>
> Review on the patch and merging it to the trunk will be appreciated.
> I'm not sure about following two points.
>
> - Register definitions were copied from Linux : include/linux/sm501-regs.h
I'd try to suck it into the .c file because the definitions are not
going to be used anywhere else in qemu.
> - Function prototype is put into "into hw/devices.h". Is it right place?
It's okay I think.
>
> Regards,
> Shin-ichiro KAWASAKI
>
> Signed-off-by: Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp>
>
> Index: trunk/Makefile.target
> ===================================================================
> --- trunk/Makefile.target (revision 5594)
> +++ trunk/Makefile.target (working copy)
> @@ -725,7 +725,7 @@
> endif
> ifeq ($(TARGET_BASE_ARCH), sh4)
> OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
> -OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o
> +OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o
> endif
> ifeq ($(TARGET_BASE_ARCH), m68k)
> OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
> Index: trunk/hw/r2d.c
> ===================================================================
> --- trunk/hw/r2d.c (revision 5594)
> +++ trunk/hw/r2d.c (working copy)
> @@ -25,6 +25,7 @@
>
> #include "hw.h"
> #include "sh.h"
> +#include "devices.h"
> #include "sysemu.h"
> #include "boards.h"
>
> @@ -148,6 +149,7 @@
> /* Register peripherals */
> r2d_fpga_init(0x04000000);
> s = sh7750_init(env);
> + sm501_init(ds, 0x10000000, (8*1024*1024));
> /* Todo: register on board registers */
> {
> int kernel_size;
> Index: trunk/hw/sm501.c
> ===================================================================
> --- trunk/hw/sm501.c (revision 0)
> +++ trunk/hw/sm501.c (revision 0)
> @@ -0,0 +1,702 @@
> +/*
> + * QEMU SM501 Device
> + *
> + * Copyright (c) 2008 Shin-ichiro KAWASAKI
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include <stdio.h>
> +#include <assert.h>
> +#include "hw.h"
> +#include "console.h"
> +#include "vga_int.h"
I think <vga_int.h> isn't needed?
> +#include "sm501-regs.h"
> +
> +/*
> + * Status: 2008/11/02
> + * - Minimum implementation for Linux console : mmio regs and CRT layer.
> + * - Always updates full screen.
> + *
> + * TODO:
> + * - Panel support
> + * - Hardware cursor support
> + * - Touch panel support
> + * - USB support
> + * - UART support
> + * - Performance tuning
> + */
> +
> +//#define DEBUG_SM501
> +//#define DEBUG_BITBLT
> +
> +#ifdef DEBUG_SM501
> +#define SM501_DPRINTF(fmt...) printf(fmt)
> +#else
> +#define SM501_DPRINTF(fmt...) do {} while(0)
> +#endif
> +
> +
> +#define MMIO_BASE_OFFSET 0x3e00000
> +
> +#define UART_RX_OFFSET 0x00
> +#define UART_TX_OFFSET 0x00
> +#define UART_IER_OFFSET 0x04
> +#define UART_IIR_OFFSET 0x08
> +#define UART_FCR_OFFSET 0x08
> +#define UART_LCR_OFFSET 0x0C
> +#define UART_MCR_OFFSET 0x10
> +#define UART_LSR_OFFSET 0x14
> +#define UART_MSR_OFFSET 0x18
> +#define UART_SCR_OFFSET 0x1C
> +
> +/* taken from "linux/drivers/mfd/sm501.c" */
> +static uint32_t sm501_mem_local_size[] = {
> + [0] = 4*1024*1024,
> + [1] = 8*1024*1024,
> + [2] = 16*1024*1024,
> + [3] = 32*1024*1024,
> + [4] = 64*1024*1024,
> + [5] = 2*1024*1024,
> +};
> +#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
> +
> +typedef struct SM501State {
> + /* graphic console status */
> + DisplayState *ds;
> + QEMUConsole *console;
> +
> + /* status & internal resources */
> + target_phys_addr_t base;
> + uint32_t local_mem_size_index;
> + uint8_t * local_mem;
> + uint32_t last_width;
> + uint32_t last_height;
> +
> + /* mmio registers */
> + uint32_t system_control;
> + uint32_t misc_control;
> + uint32_t gpio_31_0_control;
> + uint32_t gpio_63_32_control;
> + uint32_t dram_control;
> + uint32_t irq_mask;
> + uint32_t misc_timing;
> + uint32_t power_mode_control;
> +
> + uint32_t uart0_ier;
> + uint32_t uart0_lcr;
> + uint32_t uart0_mcr;
> + uint32_t uart0_scr;
> +
> + uint8_t dc_panel_palette[0x400];
> + uint8_t dc_video_palette[0x400];
> + uint8_t dc_crt_palette[0x400];
> +
> + uint32_t dc_panel_control;
> + uint32_t dc_panel_panning_control;
> + uint32_t dc_panel_fb_addr;
> + uint32_t dc_panel_fb_offset;
> + uint32_t dc_panel_fb_width;
> + uint32_t dc_panel_fb_height;
> + uint32_t dc_panel_tl_location;
> + uint32_t dc_panel_br_location;
> + uint32_t dc_panel_h_total;
> + uint32_t dc_panel_h_sync;
> + uint32_t dc_panel_v_total;
> + uint32_t dc_panel_v_sync;
> +
> + uint32_t dc_panel_hwc_addr;
> + uint32_t dc_panel_hwc_location;
> + uint32_t dc_panel_hwc_color_1_2;
> + uint32_t dc_panel_hwc_color_3;
> +
> + uint32_t dc_crt_control;
> + uint32_t dc_crt_fb_addr;
> + uint32_t dc_crt_fb_offset;
> + uint32_t dc_crt_h_total;
> + uint32_t dc_crt_h_sync;
> + uint32_t dc_crt_v_total;
> + uint32_t dc_crt_v_sync;
> +
> + uint32_t dc_crt_hwc_addr;
> + uint32_t dc_crt_hwc_location;
> + uint32_t dc_crt_hwc_color_1_2;
> + uint32_t dc_crt_hwc_color_3;
> +
> +} SM501State;
> +
> +static uint32_t get_local_mem_size_index(uint32_t size)
> +{
> + uint32_t norm_size = 0;
> + int i, index = 0;
> +
> + for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) {
> + uint32_t new_size = sm501_mem_local_size[i];
> + if (new_size >= size) {
> + if (norm_size == 0 || norm_size > new_size) {
> + norm_size = new_size;
> + index = i;
> + }
> + }
> + }
> +
> + return index;
> +}
> +
> +static uint32_t sm501_mmio_read(void *opaque, target_phys_addr_t addr)
> +{
> + SM501State * s = (SM501State *)opaque;
> + uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
> + uint32_t ret = 0;
> + SM501_DPRINTF("sm501 read addr=%x, offset=%x\n", addr, offset);
> +
> + if (SM501_DC + SM501_DC_PANEL_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_VIDEO_PALETTE) {
> + offset -= SM501_DC + SM501_DC_PANEL_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + ret = *(uint32_t*)&s->dc_panel_palette[offset];
> + } else if (SM501_DC + SM501_DC_VIDEO_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_CRT_PALETTE) {
> + offset -= SM501_DC + SM501_DC_VIDEO_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + ret = *(uint32_t*)&s->dc_video_palette[offset];
> + } else if (SM501_DC + SM501_DC_CRT_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_CRT_PALETTE + 0x400) {
> + offset -= SM501_DC + SM501_DC_CRT_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + ret = *(uint32_t*)&s->dc_crt_palette[offset];
> + } else {
> + switch(offset) {
> + case SM501_SYSTEM_CONTROL:
> + ret = s->system_control;
> + break;
> + case SM501_MISC_CONTROL:
> + ret = s->misc_control;
> + break;
> + case SM501_GPIO31_0_CONTROL:
> + ret = s->gpio_31_0_control;
> + break;
> + case SM501_GPIO63_32_CONTROL:
> + ret = s->gpio_63_32_control;
> + break;
> + case SM501_DEVICEID:
> + ret = 0x050100A0;
> + break;
> + case SM501_DRAM_CONTROL:
> + ret = (s->dram_control & 0x07F107C0)
> + | s->local_mem_size_index << 13;
> + break;
> + case SM501_IRQ_MASK:
> + ret = s->irq_mask;
> + break;
> + case SM501_MISC_TIMING:
> + /* TODO : simulate gate control */
> + ret = s->misc_timing;
> + break;
> + case SM501_CURRENT_GATE:
> + /* TODO : simulate gate control */
> + ret = 0x00021807;
> + break;
> + case SM501_CURRENT_CLOCK:
> + ret = 0x2A1A0A09;
> + break;
> + case SM501_POWER_MODE_CONTROL:
> + ret = s->power_mode_control;
> + break;
> +
> + /* TODO : implement SM501 UART */
> + case SM501_UART0 + UART_RX_OFFSET:
> + ret = 0;
> + break;
> + case SM501_UART0 + UART_IER_OFFSET:
> + ret = s->uart0_ier;
> + break;
> + case SM501_UART0 + UART_IIR_OFFSET:
> + ret = 0x01;
> + break;
> + case SM501_UART0 + UART_LCR_OFFSET:
> + ret = s->uart0_lcr;
> + break;
> + case SM501_UART0 + UART_MCR_OFFSET:
> + ret = s->uart0_mcr;
> + break;
> + case SM501_UART0 + UART_SCR_OFFSET:
> + ret = s->uart0_scr;
> + break;
> +
> + case SM501_DC + SM501_DC_PANEL_CONTROL:
> + ret = s->dc_panel_control;
> + break;
> + case SM501_DC + SM501_DC_PANEL_PANNING_CONTROL:
> + ret = s->dc_panel_panning_control;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_ADDR:
> + ret = s->dc_panel_fb_addr;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_OFFSET:
> + ret = s->dc_panel_fb_offset;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_WIDTH:
> + ret = s->dc_panel_fb_width;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_HEIGHT:
> + ret = s->dc_panel_fb_height;
> + break;
> + case SM501_DC + SM501_DC_PANEL_TL_LOC:
> + ret = s->dc_panel_tl_location;
> + break;
> + case SM501_DC + SM501_DC_PANEL_BR_LOC:
> + ret = s->dc_panel_br_location;
> + break;
> +
> + case SM501_DC + SM501_DC_PANEL_H_TOT:
> + ret = s->dc_panel_h_total;
> + break;
> + case SM501_DC + SM501_DC_PANEL_H_SYNC:
> + ret = s->dc_panel_h_sync;
> + break;
> + case SM501_DC + SM501_DC_PANEL_V_TOT:
> + ret = s->dc_panel_v_total;
> + break;
> + case SM501_DC + SM501_DC_PANEL_V_SYNC:
> + ret = s->dc_panel_v_sync;
> + break;
> +
> + case SM501_DC + SM501_DC_CRT_CONTROL:
> + ret = s->dc_crt_control;
> + break;
> + case SM501_DC + SM501_DC_CRT_FB_ADDR:
> + ret = s->dc_crt_fb_addr;
> + break;
> + case SM501_DC + SM501_DC_CRT_FB_OFFSET:
> + ret = s->dc_crt_fb_offset;
> + break;
> + case SM501_DC + SM501_DC_CRT_H_TOT:
> + ret = s->dc_crt_h_total;
> + break;
> + case SM501_DC + SM501_DC_CRT_H_SYNC:
> + ret = s->dc_crt_h_sync;
> + break;
> + case SM501_DC + SM501_DC_CRT_V_TOT:
> + ret = s->dc_crt_v_total;
> + break;
> + case SM501_DC + SM501_DC_CRT_V_SYNC:
> + ret = s->dc_crt_v_sync;
> + break;
> +
> + case SM501_DC + SM501_DC_CRT_HWC_ADDR:
> + ret = s->dc_crt_hwc_addr;
> + break;
> + case SM501_DC + SM501_DC_CRT_HWC_LOC:
> + ret = s->dc_crt_hwc_addr;
> + break;
> + case SM501_DC + SM501_DC_CRT_HWC_COLOR_1_2:
> + ret = s->dc_crt_hwc_addr;
> + break;
> + case SM501_DC + SM501_DC_CRT_HWC_COLOR_3:
> + ret = s->dc_crt_hwc_addr;
> + break;
> +
> + default:
> + printf("sm501 not implement read addr=%x, offset=%x\n",
> + addr, offset);
> + assert(0);
> + }
> + }
> + return ret;
> +}
> +
> +static uint32_t sm501_mmio_readb(void *opaque, target_phys_addr_t addr)
> +{
> + return sm501_mmio_read(opaque, addr);
> +}
> +
> +static uint32_t sm501_mmio_readw(void *opaque, target_phys_addr_t addr)
> +{
> + return sm501_mmio_read(opaque, addr);
> +}
> +
> +static uint32_t sm501_mmio_readl(void *opaque, target_phys_addr_t addr)
> +{
> + return sm501_mmio_read(opaque, addr);
> +}
> +
> +static void sm501_mmio_write(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + SM501State * s = (SM501State *)opaque;
> + uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
> + SM501_DPRINTF("sm501 write addr=%x, ofs=%x, val=%x\n",
> + addr, offset, value);
> +
> + if (SM501_DC + SM501_DC_PANEL_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_VIDEO_PALETTE) {
> + offset -= SM501_DC + SM501_DC_PANEL_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + *(uint32_t*)&s->dc_panel_palette[offset] = value;
> + } else if (SM501_DC + SM501_DC_VIDEO_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_CRT_PALETTE) {
> + offset -= SM501_DC + SM501_DC_VIDEO_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + *(uint32_t*)&s->dc_video_palette[offset] = value;
> + } else if (SM501_DC + SM501_DC_CRT_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_CRT_PALETTE + 0x400) {
> + offset -= SM501_DC + SM501_DC_CRT_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + *(uint32_t*)&s->dc_crt_palette[offset] = value;
> + } else {
> + switch(offset) {
> + case SM501_SYSTEM_CONTROL:
> + s->system_control = value & 0xE300B8F7;
> + break;
> + case SM501_MISC_CONTROL:
> + s->misc_control = value & 0xFF7FFF20;
> + break;
> + case SM501_GPIO31_0_CONTROL:
> + s->gpio_31_0_control = value;
> + break;
> + case SM501_GPIO63_32_CONTROL:
> + s->gpio_63_32_control = value;
> + break;
> + case SM501_DRAM_CONTROL:
> + s->local_mem_size_index = (value >> 13) & 0x7;
> + /* TODO : check validity of size change */
> + s->dram_control |= value & 0x7FFFFFC3;
> + break;
> + case SM501_IRQ_MASK:
> + s->irq_mask = value;
> + break;
> + case SM501_MISC_TIMING:
> + s->misc_timing = value & 0xF31F1FFF;
> + break;
> + case SM501_POWER_MODE_0_GATE:
> + case SM501_POWER_MODE_1_GATE:
> + case SM501_POWER_MODE_0_CLOCK:
> + case SM501_POWER_MODE_1_CLOCK:
> + /* TODO : simulate gate & clock control */
> + break;
> + case SM501_POWER_MODE_CONTROL:
> + s->power_mode_control = value & 0x00000003;
> + break;
> +
> + /* TODO : implement SM501 UART */
> + case SM501_UART0 + UART_IER_OFFSET:
> + s->uart0_ier = value & 0xef;
> + break;
> + case SM501_UART0 + UART_FCR_OFFSET:
> + /* throw it away */
> + break;
> + case SM501_UART0 + UART_LCR_OFFSET:
> + s->uart0_lcr = value & 0xff;
> + break;
> + case SM501_UART0 + UART_MCR_OFFSET:
> + s->uart0_mcr = value & 0x5f;
> + break;
> + case SM501_UART0 + UART_SCR_OFFSET:
> + s->uart0_scr = value & 0xff;
> + break;
> +
> + case SM501_DC + SM501_DC_PANEL_CONTROL:
> + s->dc_panel_control = value & 0x0FFF73FF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_PANNING_CONTROL:
> + s->dc_panel_panning_control = value & 0xFF3FFF3F;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_ADDR:
> + s->dc_panel_fb_addr = value & 0x8FFFFFF0;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_OFFSET:
> + s->dc_panel_fb_offset = value & 0x3FF03FF0;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_WIDTH:
> + s->dc_panel_fb_width = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_FB_HEIGHT:
> + s->dc_panel_fb_height = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_TL_LOC:
> + s->dc_panel_tl_location = value & 0x07FF07FF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_BR_LOC:
> + s->dc_panel_br_location = value & 0x07FF07FF;
> + break;
> +
> + case SM501_DC + SM501_DC_PANEL_H_TOT:
> + s->dc_panel_h_total = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_H_SYNC:
> + s->dc_panel_h_sync = value & 0x00FF0FFF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_V_TOT:
> + s->dc_panel_v_total = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_V_SYNC:
> + s->dc_panel_v_sync = value & 0x003F0FFF;
> + break;
> +
> + case SM501_DC + SM501_DC_PANEL_HWC_ADDR:
> + s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
> + break;
> + case SM501_DC + SM501_DC_PANEL_HWC_LOC:
> + s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_PANEL_HWC_COLOR_1_2:
> + s->dc_panel_hwc_addr = value;
> + break;
> + case SM501_DC + SM501_DC_PANEL_HWC_COLOR_3:
> + s->dc_panel_hwc_addr = value & 0x0000FFFF;
> + break;
> +
> + case SM501_DC + SM501_DC_CRT_CONTROL:
> + s->dc_crt_control = value & 0x0003FFFF;
> + break;
> + case SM501_DC + SM501_DC_CRT_FB_ADDR:
> + s->dc_crt_fb_addr = value & 0x8FFFFFF0;
> + break;
> + case SM501_DC + SM501_DC_CRT_FB_OFFSET:
> + s->dc_crt_fb_offset = value & 0x3FF03FF0;
> + break;
> + case SM501_DC + SM501_DC_CRT_H_TOT:
> + s->dc_crt_h_total = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_CRT_H_SYNC:
> + s->dc_crt_h_sync = value & 0x00FF0FFF;
> + break;
> + case SM501_DC + SM501_DC_CRT_V_TOT:
> + s->dc_crt_v_total = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_CRT_V_SYNC:
> + s->dc_crt_v_sync = value & 0x003F0FFF;
> + break;
> +
> + case SM501_DC + SM501_DC_CRT_HWC_ADDR:
> + s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
> + break;
> + case SM501_DC + SM501_DC_CRT_HWC_LOC:
> + s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
> + break;
> + case SM501_DC + SM501_DC_CRT_HWC_COLOR_1_2:
> + s->dc_crt_hwc_addr = value;
> + break;
> + case SM501_DC + SM501_DC_CRT_HWC_COLOR_3:
> + s->dc_crt_hwc_addr = value & 0x0000FFFF;
> + break;
> +
> + default:
> + printf("sm501 not implement write addr=%x, val=%x\n",
> + addr, value);
> + assert(0);
> + }
> + }
> +}
> +
> +static void sm501_mmio_writeb(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + sm501_mmio_write(opaque, addr, value);
> +}
> +
> +static void sm501_mmio_writew(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + sm501_mmio_write(opaque, addr, value);
> +}
> +
> +static void sm501_mmio_writel(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + sm501_mmio_write(opaque, addr, value);
> +}
> +
> +static CPUReadMemoryFunc *sm501_mmio_readfn[] = {
> + &sm501_mmio_readb,
> + &sm501_mmio_readw,
> + &sm501_mmio_readl,
> +};
> +
> +static CPUWriteMemoryFunc *sm501_mmio_writefn[] = {
> + &sm501_mmio_writeb,
> + &sm501_mmio_writew,
> + &sm501_mmio_writel,
> +};
> +
> +static uint32_t sm501_lm_read(void *opaque, target_phys_addr_t addr)
> +{
> + SM501State * s = (SM501State *)opaque;
> + uint32_t offset = addr - s->base;
> + return *(uint32_t*)&s->local_mem[offset];
> +}
> +
> +static uint32_t sm501_lm_readb(void *opaque, target_phys_addr_t addr)
> +{
> + return sm501_lm_read(opaque, addr);
> +}
> +
> +static uint32_t sm501_lm_readw(void *opaque, target_phys_addr_t addr)
> +{
> + return sm501_lm_read(opaque, addr);
> +}
> +
> +static uint32_t sm501_lm_readl(void *opaque, target_phys_addr_t addr)
> +{
> + return sm501_lm_read(opaque, addr);
> +}
> +
> +static void sm501_lm_write(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + SM501State * s = (SM501State *)opaque;
> + uint32_t offset = addr - s->base;
> + *(uint32_t*)&s->local_mem[offset] = value;
> +}
> +
> +static void sm501_lm_writeb(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + sm501_lm_write(opaque, addr, value);
> +}
> +
> +static void sm501_lm_writew(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + sm501_lm_write(opaque, addr, value);
> +}
> +
> +static void sm501_lm_writel(void *opaque,
> + target_phys_addr_t addr, uint32_t value)
> +{
> + sm501_lm_write(opaque, addr, value);
> +}
> +
> +static CPUReadMemoryFunc *sm501_lm_readfn[] = {
> + &sm501_lm_readb,
> + &sm501_lm_readw,
> + &sm501_lm_readl,
> +};
> +
> +static CPUWriteMemoryFunc *sm501_lm_writefn[] = {
> + &sm501_lm_writeb,
> + &sm501_lm_writew,
> + &sm501_lm_writel,
> +};
> +
> +static void sm501_draw_crt(SM501State * s)
> +{
> + int x, y;
> + uint32_t crt_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
> + uint32_t crt_height = (s->dc_crt_v_total & 0x00000FFF) + 1;
> + uint8_t * buf = s->local_mem;
> + uint32_t * palette = (uint32_t *)s->dc_crt_palette;
> +
> + /* adjust console size */
> + if (s->last_width != crt_width || s->last_height != crt_height) {
> + qemu_console_resize(s->console, crt_width, crt_height);
> + s->last_width = crt_width;
> + s->last_height = crt_height;
> + }
> +
> + switch (s->dc_crt_control & 3) {
> + case SM501_DC_CRT_CONTROL_8BPP:
> + for (y = 0; y < crt_height; y++) {
> + for (x = 0; x < crt_width; x++) {
> + int i = (y * crt_width + x) * 4;
> + *(uint32_t *)&s->ds->data[i] = palette[*buf];
> + buf++;
> + }
> + }
> + break;
> + case SM501_DC_CRT_CONTROL_16BPP:
> + for (y = 0; y < crt_height; y++) {
> + for (x = 0; x < crt_width; x++) {
> + int i = (y * crt_width + x) * 4;
> + uint32_t rgb565 = *(uint16_t*)buf;
> + int r = ((rgb565 >> 11) & 0x1f) << 3;
> + int g = ((rgb565 >> 5) & 0x3f) << 2;
> + int b = ((rgb565 >> 0) & 0x1f) << 3;
> + s->ds->data[i + 0] = b;
> + s->ds->data[i + 1] = g;
> + s->ds->data[i + 2] = r;
> + s->ds->data[i + 3] = 0;
> + buf += 2;
> + }
> + }
> + break;
> + case SM501_DC_CRT_CONTROL_32BPP:
> + for (y = 0; y < crt_height; y++) {
> + for (x = 0; x < crt_width; x++) {
> + int i = (y * crt_width + x) * 4;
> + *(uint32_t *)&s->ds->data[i] = *(uint32_t*)buf;
> + buf += 4;
> + }
> + }
> + break;
All the cases assume the host is using 32 bpp colours, which is rare I
think. Because s->ds->depth is not checked, it will likely segfault.
Cheers
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4
2008-11-02 2:12 [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4 Shin-ichiro KAWASAKI
2008-11-02 3:27 ` andrzej zaborowski
@ 2008-11-02 6:52 ` Blue Swirl
2008-11-04 15:10 ` Shin-ichiro KAWASAKI
2008-11-04 15:27 ` [Qemu-devel] When should I use qemu_ram_alloc(), and how? takasi-y
1 sibling, 2 replies; 14+ messages in thread
From: Blue Swirl @ 2008-11-02 6:52 UTC (permalink / raw)
To: qemu-devel
On 11/2/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> Hi, all!
>
> This patch adds minimum emulation of SM501 multifunction device,
> whose main feature is 2D graphics. It is one of the peripheral
> of R2D, the SH4 evaluation board. We can see TUX printed on the
> QEMU console.
> +#define UART_RX_OFFSET 0x00
> +#define UART_TX_OFFSET 0x00
> +#define UART_IER_OFFSET 0x04
> +#define UART_IIR_OFFSET 0x08
> +#define UART_FCR_OFFSET 0x08
> +#define UART_LCR_OFFSET 0x0C
> +#define UART_MCR_OFFSET 0x10
> +#define UART_LSR_OFFSET 0x14
> +#define UART_MSR_OFFSET 0x18
> +#define UART_SCR_OFFSET 0x1C
Looks like standard 16550-like UART. Maybe you could use the version
in serial.c and map that to this location?
> +/* taken from "linux/drivers/mfd/sm501.c" */
> +static uint32_t sm501_mem_local_size[] = {
"const"?
> + if (SM501_DC + SM501_DC_PANEL_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_VIDEO_PALETTE) {
> + offset -= SM501_DC + SM501_DC_PANEL_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + ret = *(uint32_t*)&s->dc_panel_palette[offset];
> + } else if (SM501_DC + SM501_DC_VIDEO_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_CRT_PALETTE) {
> + offset -= SM501_DC + SM501_DC_VIDEO_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + ret = *(uint32_t*)&s->dc_video_palette[offset];
> + } else if (SM501_DC + SM501_DC_CRT_PALETTE <= offset
> + && offset < SM501_DC + SM501_DC_CRT_PALETTE + 0x400) {
> + offset -= SM501_DC + SM501_DC_CRT_PALETTE;
> + /* TODO : consider BYTE/WORD access */
> + /* TODO : consider endian */
> + ret = *(uint32_t*)&s->dc_crt_palette[offset];
> + } else {
The above should be cleaner and faster if you registered different
access routines for each area.
> +static uint32_t sm501_lm_read(void *opaque, target_phys_addr_t addr)
> +{
> + SM501State * s = (SM501State *)opaque;
> + uint32_t offset = addr - s->base;
> + return *(uint32_t*)&s->local_mem[offset];
> +}
It would be much faster to register normal RAM for this area and check
for updated pages asynchronously using VGA_DIRTY_FLAG (see vga.c or
tcx.c).
> + /* allocate local memory */
> + s->local_mem = qemu_mallocz(get_local_mem_size(s));
The display buffer should be allocated using machine definition .ram_require.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4
2008-11-02 3:27 ` andrzej zaborowski
@ 2008-11-04 14:31 ` Shin-ichiro KAWASAKI
0 siblings, 0 replies; 14+ messages in thread
From: Shin-ichiro KAWASAKI @ 2008-11-04 14:31 UTC (permalink / raw)
To: qemu-devel
Thank you for your review!
>> I'm not sure about following two points.
>>
>> - Register definitions were copied from Linux : include/linux/sm501-regs.h
>
> I'd try to suck it into the .c file because the definitions are not
> going to be used anywhere else in qemu.
OK. I'll include it in sm501.c.
>> +#include "vga_int.h"
>
> I think <vga_int.h> isn't needed?
Right. Will be deleted.
>> +static void sm501_draw_crt(SM501State * s)
>> +{
>> + int x, y;
>> + uint32_t crt_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
>> + uint32_t crt_height = (s->dc_crt_v_total & 0x00000FFF) + 1;
>> + uint8_t * buf = s->local_mem;
>> + uint32_t * palette = (uint32_t *)s->dc_crt_palette;
>> +
>> + /* adjust console size */
>> + if (s->last_width != crt_width || s->last_height != crt_height) {
>> + qemu_console_resize(s->console, crt_width, crt_height);
>> + s->last_width = crt_width;
>> + s->last_height = crt_height;
>> + }
>> +
>> + switch (s->dc_crt_control & 3) {
>> + case SM501_DC_CRT_CONTROL_8BPP:
>> + for (y = 0; y < crt_height; y++) {
>> + for (x = 0; x < crt_width; x++) {
>> + int i = (y * crt_width + x) * 4;
>> + *(uint32_t *)&s->ds->data[i] = palette[*buf];
>> + buf++;
>> + }
>> + }
>> + break;
>> + case SM501_DC_CRT_CONTROL_16BPP:
>> + for (y = 0; y < crt_height; y++) {
>> + for (x = 0; x < crt_width; x++) {
>> + int i = (y * crt_width + x) * 4;
>> + uint32_t rgb565 = *(uint16_t*)buf;
>> + int r = ((rgb565 >> 11) & 0x1f) << 3;
>> + int g = ((rgb565 >> 5) & 0x3f) << 2;
>> + int b = ((rgb565 >> 0) & 0x1f) << 3;
>> + s->ds->data[i + 0] = b;
>> + s->ds->data[i + 1] = g;
>> + s->ds->data[i + 2] = r;
>> + s->ds->data[i + 3] = 0;
>> + buf += 2;
>> + }
>> + }
>> + break;
>> + case SM501_DC_CRT_CONTROL_32BPP:
>> + for (y = 0; y < crt_height; y++) {
>> + for (x = 0; x < crt_width; x++) {
>> + int i = (y * crt_width + x) * 4;
>> + *(uint32_t *)&s->ds->data[i] = *(uint32_t*)buf;
>> + buf += 4;
>> + }
>> + }
>> + break;
>
> All the cases assume the host is using 32 bpp colours, which is rare I
> think. Because s->ds->depth is not checked, it will likely segfault.
Right. I will introduce templates like hw/vga_template.h to fit
s->ds->depth variety.
Thanks!
Shin-ichiro KAWASAKI
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4
2008-11-02 6:52 ` Blue Swirl
@ 2008-11-04 15:10 ` Shin-ichiro KAWASAKI
2008-11-04 19:11 ` Blue Swirl
2008-11-04 15:27 ` [Qemu-devel] When should I use qemu_ram_alloc(), and how? takasi-y
1 sibling, 1 reply; 14+ messages in thread
From: Shin-ichiro KAWASAKI @ 2008-11-04 15:10 UTC (permalink / raw)
To: qemu-devel
Thank you for reviewing!
I add the new version of patch to this mail, which reflects
you and andrzej's comments. Some more comments on it will be
appreciated. Especially advice on VRAM implementation with
normal RAM will be useful for me.
>> +#define UART_RX_OFFSET 0x00
>> +#define UART_TX_OFFSET 0x00
>> +#define UART_IER_OFFSET 0x04
>> +#define UART_IIR_OFFSET 0x08
>> +#define UART_FCR_OFFSET 0x08
>> +#define UART_LCR_OFFSET 0x0C
>> +#define UART_MCR_OFFSET 0x10
>> +#define UART_LSR_OFFSET 0x14
>> +#define UART_MSR_OFFSET 0x18
>> +#define UART_SCR_OFFSET 0x1C
>
> Looks like standard 16550-like UART. Maybe you could use the version
> in serial.c and map that to this location?
Right, I did so in the new patch.
>> +/* taken from "linux/drivers/mfd/sm501.c" */
>> +static uint32_t sm501_mem_local_size[] = {
>
> "const"?
It should be.
>> + if (SM501_DC + SM501_DC_PANEL_PALETTE <= offset
>> + && offset < SM501_DC + SM501_DC_VIDEO_PALETTE) {
>> + offset -= SM501_DC + SM501_DC_PANEL_PALETTE;
>> + /* TODO : consider BYTE/WORD access */
>> + /* TODO : consider endian */
>> + ret = *(uint32_t*)&s->dc_panel_palette[offset];
>> + } else if (SM501_DC + SM501_DC_VIDEO_PALETTE <= offset
>> + && offset < SM501_DC + SM501_DC_CRT_PALETTE) {
>> + offset -= SM501_DC + SM501_DC_VIDEO_PALETTE;
>> + /* TODO : consider BYTE/WORD access */
>> + /* TODO : consider endian */
>> + ret = *(uint32_t*)&s->dc_video_palette[offset];
>> + } else if (SM501_DC + SM501_DC_CRT_PALETTE <= offset
>> + && offset < SM501_DC + SM501_DC_CRT_PALETTE + 0x400) {
>> + offset -= SM501_DC + SM501_DC_CRT_PALETTE;
>> + /* TODO : consider BYTE/WORD access */
>> + /* TODO : consider endian */
>> + ret = *(uint32_t*)&s->dc_crt_palette[offset];
>> + } else {
>
> The above should be cleaner and faster if you registered different
> access routines for each area.
Right. I divided SM501 registers into some parts and registered each of them.
To say it correctly about the palettes, I merged these three palettes into one
memory region to avoid messy codes.
>> +static uint32_t sm501_lm_read(void *opaque, target_phys_addr_t addr)
>> +{
>> + SM501State * s = (SM501State *)opaque;
>> + uint32_t offset = addr - s->base;
>> + return *(uint32_t*)&s->local_mem[offset];
>> +}
>
> It would be much faster to register normal RAM for this area and check
> for updated pages asynchronously using VGA_DIRTY_FLAG (see vga.c or
> tcx.c).
Thanks for the advice, but following problem blocks to realize it.
>> + /* allocate local memory */
>> + s->local_mem = qemu_mallocz(get_local_mem_size(s));
>
> The display buffer should be allocated using machine definition .ram_require.
I tried normal RAM implementation : "#define USE_NORMAL_RAM" in the patch will
turn the new implementation on. But it causes system hang during SH-Linux boot up.
The initial VRAM clearance seems to cause the hang.
The reason might be my wrong implementation, or any MMU problem of SH4.
I did,
- added VRAM size to .ram_require
- invoked qemu_ram_alloc() with the VRAM size parameter,
- and invoked cpu_register_physical_memory(), passing the return value of
qemu_ram_alloc() as third parameter.
Is this sequence correct?
Regards,
Shin-ichiro KAWASAKI
Index: trunk/Makefile.target
===================================================================
--- trunk/Makefile.target (revision 5594)
+++ trunk/Makefile.target (working copy)
@@ -725,7 +725,7 @@
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
-OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o
+OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o serial.o
endif
ifeq ($(TARGET_BASE_ARCH), m68k)
OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
Index: trunk/hw/r2d.c
===================================================================
--- trunk/hw/r2d.c (revision 5594)
+++ trunk/hw/r2d.c (working copy)
@@ -25,12 +25,15 @@
#include "hw.h"
#include "sh.h"
+#include "devices.h"
#include "sysemu.h"
#include "boards.h"
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000
+#define SM501_VRAM_SIZE 0x800000
+
#define PA_POWOFF 0x30
#define PA_VERREG 0x32
#define PA_OUTPORT 0x36
@@ -133,6 +136,7 @@
{
CPUState *env;
struct SH7750State *s;
+ ram_addr_t sm501_vga_ram_addr;
if (!cpu_model)
cpu_model = "SH7751R";
@@ -148,6 +152,9 @@
/* Register peripherals */
r2d_fpga_init(0x04000000);
s = sh7750_init(env);
+ sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
+ sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
+ serial_hds[2]);
/* Todo: register on board registers */
{
int kernel_size;
@@ -167,5 +174,5 @@
.name = "r2d",
.desc = "r2d-plus board",
.init = r2d_init,
- .ram_require = SDRAM_SIZE | RAMSIZE_FIXED,
+ .ram_require = (SDRAM_SIZE + SM501_VRAM_SIZE) | RAMSIZE_FIXED,
};
Index: trunk/hw/sm501.c
===================================================================
--- trunk/hw/sm501.c (revision 0)
+++ trunk/hw/sm501.c (revision 0)
@@ -0,0 +1,1164 @@
+/*
+ * QEMU SM501 Device
+ *
+ * Copyright (c) 2008 Shin-ichiro KAWASAKI
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <assert.h>
+#include "hw.h"
+#include "pc.h"
+#include "console.h"
+
+/*
+ * Status: 2008/11/02
+ * - Minimum implementation for Linux console : mmio regs and CRT layer.
+ * - Always updates full screen.
+ *
+ * TODO:
+ * - Panel support
+ * - Hardware cursor support
+ * - Touch panel support
+ * - USB support
+ * - UART support
+ * - Performance tuning
+ */
+
+//#define DEBUG_SM501
+//#define DEBUG_BITBLT
+
+/* Temporary option. Should be elminated in the future. */
+#undef USE_NORMAL_RAM
+
+#ifdef DEBUG_SM501
+#define SM501_DPRINTF(fmt...) printf(fmt)
+#else
+#define SM501_DPRINTF(fmt...) do {} while(0)
+#endif
+
+
+#define MMIO_BASE_OFFSET 0x3e00000
+
+/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
+
+/* System Configuration area */
+/* System config base */
+#define SM501_SYS_CONFIG (0x000000)
+
+/* config 1 */
+#define SM501_SYSTEM_CONTROL (0x000000)
+
+#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
+#define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
+#define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
+
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
+
+#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
+#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
+#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
+#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
+
+/* miscellaneous control */
+
+#define SM501_MISC_CONTROL (0x000004)
+
+#define SM501_MISC_BUS_SH (0x0)
+#define SM501_MISC_BUS_PCI (0x1)
+#define SM501_MISC_BUS_XSCALE (0x2)
+#define SM501_MISC_BUS_NEC (0x6)
+#define SM501_MISC_BUS_MASK (0x7)
+
+#define SM501_MISC_VR_62MB (1<<3)
+#define SM501_MISC_CDR_RESET (1<<7)
+#define SM501_MISC_USB_LB (1<<8)
+#define SM501_MISC_USB_SLAVE (1<<9)
+#define SM501_MISC_BL_1 (1<<10)
+#define SM501_MISC_MC (1<<11)
+#define SM501_MISC_DAC_POWER (1<<12)
+#define SM501_MISC_IRQ_INVERT (1<<16)
+#define SM501_MISC_SH (1<<17)
+
+#define SM501_MISC_HOLD_EMPTY (0<<18)
+#define SM501_MISC_HOLD_8 (1<<18)
+#define SM501_MISC_HOLD_16 (2<<18)
+#define SM501_MISC_HOLD_24 (3<<18)
+#define SM501_MISC_HOLD_32 (4<<18)
+#define SM501_MISC_HOLD_MASK (7<<18)
+
+#define SM501_MISC_FREQ_12 (1<<24)
+#define SM501_MISC_PNL_24BIT (1<<25)
+#define SM501_MISC_8051_LE (1<<26)
+
+
+
+#define SM501_GPIO31_0_CONTROL (0x000008)
+#define SM501_GPIO63_32_CONTROL (0x00000C)
+#define SM501_DRAM_CONTROL (0x000010)
+
+/* command list */
+#define SM501_ARBTRTN_CONTROL (0x000014)
+
+/* command list */
+#define SM501_COMMAND_LIST_STATUS (0x000024)
+
+/* interrupt debug */
+#define SM501_RAW_IRQ_STATUS (0x000028)
+#define SM501_RAW_IRQ_CLEAR (0x000028)
+#define SM501_IRQ_STATUS (0x00002C)
+#define SM501_IRQ_MASK (0x000030)
+#define SM501_DEBUG_CONTROL (0x000034)
+
+/* power management */
+#define SM501_POWERMODE_P2X_SRC (1<<29)
+#define SM501_POWERMODE_V2X_SRC (1<<20)
+#define SM501_POWERMODE_M_SRC (1<<12)
+#define SM501_POWERMODE_M1_SRC (1<<4)
+
+#define SM501_CURRENT_GATE (0x000038)
+#define SM501_CURRENT_CLOCK (0x00003C)
+#define SM501_POWER_MODE_0_GATE (0x000040)
+#define SM501_POWER_MODE_0_CLOCK (0x000044)
+#define SM501_POWER_MODE_1_GATE (0x000048)
+#define SM501_POWER_MODE_1_CLOCK (0x00004C)
+#define SM501_SLEEP_MODE_GATE (0x000050)
+#define SM501_POWER_MODE_CONTROL (0x000054)
+
+/* power gates for units within the 501 */
+#define SM501_GATE_HOST (0)
+#define SM501_GATE_MEMORY (1)
+#define SM501_GATE_DISPLAY (2)
+#define SM501_GATE_2D_ENGINE (3)
+#define SM501_GATE_CSC (4)
+#define SM501_GATE_ZVPORT (5)
+#define SM501_GATE_GPIO (6)
+#define SM501_GATE_UART0 (7)
+#define SM501_GATE_UART1 (8)
+#define SM501_GATE_SSP (10)
+#define SM501_GATE_USB_HOST (11)
+#define SM501_GATE_USB_GADGET (12)
+#define SM501_GATE_UCONTROLLER (17)
+#define SM501_GATE_AC97 (18)
+
+/* panel clock */
+#define SM501_CLOCK_P2XCLK (24)
+/* crt clock */
+#define SM501_CLOCK_V2XCLK (16)
+/* main clock */
+#define SM501_CLOCK_MCLK (8)
+/* SDRAM controller clock */
+#define SM501_CLOCK_M1XCLK (0)
+
+/* config 2 */
+#define SM501_PCI_MASTER_BASE (0x000058)
+#define SM501_ENDIAN_CONTROL (0x00005C)
+#define SM501_DEVICEID (0x000060)
+/* 0x050100A0 */
+
+#define SM501_DEVICEID_SM501 (0x05010000)
+#define SM501_DEVICEID_IDMASK (0xffff0000)
+#define SM501_DEVICEID_REVMASK (0x000000ff)
+
+#define SM501_PLLCLOCK_COUNT (0x000064)
+#define SM501_MISC_TIMING (0x000068)
+#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
+
+#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
+
+/* GPIO base */
+#define SM501_GPIO (0x010000)
+#define SM501_GPIO_DATA_LOW (0x00)
+#define SM501_GPIO_DATA_HIGH (0x04)
+#define SM501_GPIO_DDR_LOW (0x08)
+#define SM501_GPIO_DDR_HIGH (0x0C)
+#define SM501_GPIO_IRQ_SETUP (0x10)
+#define SM501_GPIO_IRQ_STATUS (0x14)
+#define SM501_GPIO_IRQ_RESET (0x14)
+
+/* I2C controller base */
+#define SM501_I2C (0x010040)
+#define SM501_I2C_BYTE_COUNT (0x00)
+#define SM501_I2C_CONTROL (0x01)
+#define SM501_I2C_STATUS (0x02)
+#define SM501_I2C_RESET (0x02)
+#define SM501_I2C_SLAVE_ADDRESS (0x03)
+#define SM501_I2C_DATA (0x04)
+
+/* SSP base */
+#define SM501_SSP (0x020000)
+
+/* Uart 0 base */
+#define SM501_UART0 (0x030000)
+
+/* Uart 1 base */
+#define SM501_UART1 (0x030020)
+
+/* USB host port base */
+#define SM501_USB_HOST (0x040000)
+
+/* USB slave/gadget base */
+#define SM501_USB_GADGET (0x060000)
+
+/* USB slave/gadget data port base */
+#define SM501_USB_GADGET_DATA (0x070000)
+
+/* Display controller/video engine base */
+#define SM501_DC (0x080000)
+
+/* common defines for the SM501 address registers */
+#define SM501_ADDR_FLIP (1<<31)
+#define SM501_ADDR_EXT (1<<27)
+#define SM501_ADDR_CS1 (1<<26)
+#define SM501_ADDR_MASK (0x3f << 26)
+
+#define SM501_FIFO_MASK (0x3 << 16)
+#define SM501_FIFO_1 (0x0 << 16)
+#define SM501_FIFO_3 (0x1 << 16)
+#define SM501_FIFO_7 (0x2 << 16)
+#define SM501_FIFO_11 (0x3 << 16)
+
+/* common registers for panel and the crt */
+#define SM501_OFF_DC_H_TOT (0x000)
+#define SM501_OFF_DC_V_TOT (0x008)
+#define SM501_OFF_DC_H_SYNC (0x004)
+#define SM501_OFF_DC_V_SYNC (0x00C)
+
+#define SM501_DC_PANEL_CONTROL (0x000)
+
+#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
+#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
+#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
+#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
+#define SM501_DC_PANEL_CONTROL_DP (1<<23)
+
+#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
+
+#define SM501_DC_PANEL_CONTROL_DE (1<<20)
+
+#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
+
+#define SM501_DC_PANEL_CONTROL_CP (1<<14)
+#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
+#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
+#define SM501_DC_PANEL_CONTROL_CK (1<<9)
+#define SM501_DC_PANEL_CONTROL_TE (1<<8)
+#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
+#define SM501_DC_PANEL_CONTROL_VP (1<<6)
+#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
+#define SM501_DC_PANEL_CONTROL_HP (1<<4)
+#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
+#define SM501_DC_PANEL_CONTROL_EN (1<<2)
+
+#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
+#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
+#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
+
+
+#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
+#define SM501_DC_PANEL_COLOR_KEY (0x008)
+#define SM501_DC_PANEL_FB_ADDR (0x00C)
+#define SM501_DC_PANEL_FB_OFFSET (0x010)
+#define SM501_DC_PANEL_FB_WIDTH (0x014)
+#define SM501_DC_PANEL_FB_HEIGHT (0x018)
+#define SM501_DC_PANEL_TL_LOC (0x01C)
+#define SM501_DC_PANEL_BR_LOC (0x020)
+#define SM501_DC_PANEL_H_TOT (0x024)
+#define SM501_DC_PANEL_H_SYNC (0x028)
+#define SM501_DC_PANEL_V_TOT (0x02C)
+#define SM501_DC_PANEL_V_SYNC (0x030)
+#define SM501_DC_PANEL_CUR_LINE (0x034)
+
+#define SM501_DC_VIDEO_CONTROL (0x040)
+#define SM501_DC_VIDEO_FB0_ADDR (0x044)
+#define SM501_DC_VIDEO_FB_WIDTH (0x048)
+#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
+#define SM501_DC_VIDEO_TL_LOC (0x050)
+#define SM501_DC_VIDEO_BR_LOC (0x054)
+#define SM501_DC_VIDEO_SCALE (0x058)
+#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
+#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
+#define SM501_DC_VIDEO_FB1_ADDR (0x064)
+#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
+
+#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
+#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
+#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
+#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
+#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
+#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
+#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
+#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
+#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
+#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
+
+#define SM501_DC_PANEL_HWC_BASE (0x0F0)
+#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
+#define SM501_DC_PANEL_HWC_LOC (0x0F4)
+#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
+#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
+
+#define SM501_HWC_EN (1<<31)
+
+#define SM501_OFF_HWC_ADDR (0x00)
+#define SM501_OFF_HWC_LOC (0x04)
+#define SM501_OFF_HWC_COLOR_1_2 (0x08)
+#define SM501_OFF_HWC_COLOR_3 (0x0C)
+
+#define SM501_DC_ALPHA_CONTROL (0x100)
+#define SM501_DC_ALPHA_FB_ADDR (0x104)
+#define SM501_DC_ALPHA_FB_OFFSET (0x108)
+#define SM501_DC_ALPHA_TL_LOC (0x10C)
+#define SM501_DC_ALPHA_BR_LOC (0x110)
+#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
+#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
+
+#define SM501_DC_CRT_CONTROL (0x200)
+
+#define SM501_DC_CRT_CONTROL_TVP (1<<15)
+#define SM501_DC_CRT_CONTROL_CP (1<<14)
+#define SM501_DC_CRT_CONTROL_VSP (1<<13)
+#define SM501_DC_CRT_CONTROL_HSP (1<<12)
+#define SM501_DC_CRT_CONTROL_VS (1<<11)
+#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
+#define SM501_DC_CRT_CONTROL_SEL (1<<9)
+#define SM501_DC_CRT_CONTROL_TE (1<<8)
+#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
+#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
+#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
+
+#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
+#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
+#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
+
+#define SM501_DC_CRT_FB_ADDR (0x204)
+#define SM501_DC_CRT_FB_OFFSET (0x208)
+#define SM501_DC_CRT_H_TOT (0x20C)
+#define SM501_DC_CRT_H_SYNC (0x210)
+#define SM501_DC_CRT_V_TOT (0x214)
+#define SM501_DC_CRT_V_SYNC (0x218)
+#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
+#define SM501_DC_CRT_CUR_LINE (0x220)
+#define SM501_DC_CRT_MONITOR_DETECT (0x224)
+
+#define SM501_DC_CRT_HWC_BASE (0x230)
+#define SM501_DC_CRT_HWC_ADDR (0x230)
+#define SM501_DC_CRT_HWC_LOC (0x234)
+#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
+#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
+
+#define SM501_DC_PANEL_PALETTE (0x400)
+
+#define SM501_DC_VIDEO_PALETTE (0x800)
+
+#define SM501_DC_CRT_PALETTE (0xC00)
+
+/* Zoom Video port base */
+#define SM501_ZVPORT (0x090000)
+
+/* AC97/I2S base */
+#define SM501_AC97 (0x0A0000)
+
+/* 8051 micro controller base */
+#define SM501_UCONTROLLER (0x0B0000)
+
+/* 8051 micro controller SRAM base */
+#define SM501_UCONTROLLER_SRAM (0x0C0000)
+
+/* DMA base */
+#define SM501_DMA (0x0D0000)
+
+/* 2d engine base */
+#define SM501_2D_ENGINE (0x100000)
+#define SM501_2D_SOURCE (0x00)
+#define SM501_2D_DESTINATION (0x04)
+#define SM501_2D_DIMENSION (0x08)
+#define SM501_2D_CONTROL (0x0C)
+#define SM501_2D_PITCH (0x10)
+#define SM501_2D_FOREGROUND (0x14)
+#define SM501_2D_BACKGROUND (0x18)
+#define SM501_2D_STRETCH (0x1C)
+#define SM501_2D_COLOR_COMPARE (0x20)
+#define SM501_2D_COLOR_COMPARE_MASK (0x24)
+#define SM501_2D_MASK (0x28)
+#define SM501_2D_CLIP_TL (0x2C)
+#define SM501_2D_CLIP_BR (0x30)
+#define SM501_2D_MONO_PATTERN_LOW (0x34)
+#define SM501_2D_MONO_PATTERN_HIGH (0x38)
+#define SM501_2D_WINDOW_WIDTH (0x3C)
+#define SM501_2D_SOURCE_BASE (0x40)
+#define SM501_2D_DESTINATION_BASE (0x44)
+#define SM501_2D_ALPHA (0x48)
+#define SM501_2D_WRAP (0x4C)
+#define SM501_2D_STATUS (0x50)
+
+#define SM501_CSC_Y_SOURCE_BASE (0xC8)
+#define SM501_CSC_CONSTANTS (0xCC)
+#define SM501_CSC_Y_SOURCE_X (0xD0)
+#define SM501_CSC_Y_SOURCE_Y (0xD4)
+#define SM501_CSC_U_SOURCE_BASE (0xD8)
+#define SM501_CSC_V_SOURCE_BASE (0xDC)
+#define SM501_CSC_SOURCE_DIMENSION (0xE0)
+#define SM501_CSC_SOURCE_PITCH (0xE4)
+#define SM501_CSC_DESTINATION (0xE8)
+#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
+#define SM501_CSC_DESTINATION_PITCH (0xF0)
+#define SM501_CSC_SCALE_FACTOR (0xF4)
+#define SM501_CSC_DESTINATION_BASE (0xF8)
+#define SM501_CSC_CONTROL (0xFC)
+
+/* 2d engine data port base */
+#define SM501_2D_ENGINE_DATA (0x110000)
+
+/* end of register definitions */
+
+
+/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
+static const uint32_t sm501_mem_local_size[] = {
+ [0] = 4*1024*1024,
+ [1] = 8*1024*1024,
+ [2] = 16*1024*1024,
+ [3] = 32*1024*1024,
+ [4] = 64*1024*1024,
+ [5] = 2*1024*1024,
+};
+#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
+
+typedef struct SM501State {
+ /* graphic console status */
+ DisplayState *ds;
+ QEMUConsole *console;
+
+ /* status & internal resources */
+ target_phys_addr_t base;
+ uint32_t local_mem_size_index;
+ uint8_t * local_mem;
+ uint32_t last_width;
+ uint32_t last_height;
+
+ /* mmio registers */
+ uint32_t system_control;
+ uint32_t misc_control;
+ uint32_t gpio_31_0_control;
+ uint32_t gpio_63_32_control;
+ uint32_t dram_control;
+ uint32_t irq_mask;
+ uint32_t misc_timing;
+ uint32_t power_mode_control;
+
+ uint32_t uart0_ier;
+ uint32_t uart0_lcr;
+ uint32_t uart0_mcr;
+ uint32_t uart0_scr;
+
+ uint8_t dc_palette[0x400 * 3];
+
+ uint32_t dc_panel_control;
+ uint32_t dc_panel_panning_control;
+ uint32_t dc_panel_fb_addr;
+ uint32_t dc_panel_fb_offset;
+ uint32_t dc_panel_fb_width;
+ uint32_t dc_panel_fb_height;
+ uint32_t dc_panel_tl_location;
+ uint32_t dc_panel_br_location;
+ uint32_t dc_panel_h_total;
+ uint32_t dc_panel_h_sync;
+ uint32_t dc_panel_v_total;
+ uint32_t dc_panel_v_sync;
+
+ uint32_t dc_panel_hwc_addr;
+ uint32_t dc_panel_hwc_location;
+ uint32_t dc_panel_hwc_color_1_2;
+ uint32_t dc_panel_hwc_color_3;
+
+ uint32_t dc_crt_control;
+ uint32_t dc_crt_fb_addr;
+ uint32_t dc_crt_fb_offset;
+ uint32_t dc_crt_h_total;
+ uint32_t dc_crt_h_sync;
+ uint32_t dc_crt_v_total;
+ uint32_t dc_crt_v_sync;
+
+ uint32_t dc_crt_hwc_addr;
+ uint32_t dc_crt_hwc_location;
+ uint32_t dc_crt_hwc_color_1_2;
+ uint32_t dc_crt_hwc_color_3;
+
+} SM501State;
+
+static uint32_t get_local_mem_size_index(uint32_t size)
+{
+ uint32_t norm_size = 0;
+ int i, index = 0;
+
+ for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) {
+ uint32_t new_size = sm501_mem_local_size[i];
+ if (new_size >= size) {
+ if (norm_size == 0 || norm_size > new_size) {
+ norm_size = new_size;
+ index = i;
+ }
+ }
+ }
+
+ return index;
+}
+
+static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
+ uint32_t ret = 0;
+ SM501_DPRINTF("sm501 system config regs : read addr=%x, offset=%x\n",
+ addr, offset);
+
+ switch(offset) {
+ case SM501_SYSTEM_CONTROL:
+ ret = s->system_control;
+ break;
+ case SM501_MISC_CONTROL:
+ ret = s->misc_control;
+ break;
+ case SM501_GPIO31_0_CONTROL:
+ ret = s->gpio_31_0_control;
+ break;
+ case SM501_GPIO63_32_CONTROL:
+ ret = s->gpio_63_32_control;
+ break;
+ case SM501_DEVICEID:
+ ret = 0x050100A0;
+ break;
+ case SM501_DRAM_CONTROL:
+ ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
+ break;
+ case SM501_IRQ_MASK:
+ ret = s->irq_mask;
+ break;
+ case SM501_MISC_TIMING:
+ /* TODO : simulate gate control */
+ ret = s->misc_timing;
+ break;
+ case SM501_CURRENT_GATE:
+ /* TODO : simulate gate control */
+ ret = 0x00021807;
+ break;
+ case SM501_CURRENT_CLOCK:
+ ret = 0x2A1A0A09;
+ break;
+ case SM501_POWER_MODE_CONTROL:
+ ret = s->power_mode_control;
+ break;
+
+ default:
+ printf("sm501 system config : not implemented register read."
+ " addr=%x, offset=%x\n", addr, offset);
+ assert(0);
+ }
+
+ return ret;
+}
+
+static void sm501_system_config_write(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
+ SM501_DPRINTF("sm501 system config regs : write addr=%x, ofs=%x, val=%x\n",
+ addr, offset, value);
+
+ switch(offset) {
+ case SM501_SYSTEM_CONTROL:
+ s->system_control = value & 0xE300B8F7;
+ break;
+ case SM501_MISC_CONTROL:
+ s->misc_control = value & 0xFF7FFF20;
+ break;
+ case SM501_GPIO31_0_CONTROL:
+ s->gpio_31_0_control = value;
+ break;
+ case SM501_GPIO63_32_CONTROL:
+ s->gpio_63_32_control = value;
+ break;
+ case SM501_DRAM_CONTROL:
+ s->local_mem_size_index = (value >> 13) & 0x7;
+ /* rODO : check validity of size change */
+ s->dram_control |= value & 0x7FFFFFC3;
+ break;
+ case SM501_IRQ_MASK:
+ s->irq_mask = value;
+ break;
+ case SM501_MISC_TIMING:
+ s->misc_timing = value & 0xF31F1FFF;
+ break;
+ case SM501_POWER_MODE_0_GATE:
+ case SM501_POWER_MODE_1_GATE:
+ case SM501_POWER_MODE_0_CLOCK:
+ case SM501_POWER_MODE_1_CLOCK:
+ /* TODO : simulate gate & clock control */
+ break;
+ case SM501_POWER_MODE_CONTROL:
+ s->power_mode_control = value & 0x00000003;
+ break;
+
+ default:
+ printf("sm501 system config : not implemented register write."
+ " addr=%x, val=%x\n", addr, value);
+ assert(0);
+ }
+}
+
+static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
+ NULL,
+ NULL,
+ &sm501_system_config_read,
+};
+
+static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
+ NULL,
+ NULL,
+ &sm501_system_config_write,
+};
+
+static uint32_t sm501_disp_ctrl_read(void *opaque,
+ target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
+ uint32_t ret = 0;
+ SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x, offset=%x\n",
+ addr, offset);
+
+ switch(offset) {
+
+ case SM501_DC_PANEL_CONTROL:
+ ret = s->dc_panel_control;
+ break;
+ case SM501_DC_PANEL_PANNING_CONTROL:
+ ret = s->dc_panel_panning_control;
+ break;
+ case SM501_DC_PANEL_FB_ADDR:
+ ret = s->dc_panel_fb_addr;
+ break;
+ case SM501_DC_PANEL_FB_OFFSET:
+ ret = s->dc_panel_fb_offset;
+ break;
+ case SM501_DC_PANEL_FB_WIDTH:
+ ret = s->dc_panel_fb_width;
+ break;
+ case SM501_DC_PANEL_FB_HEIGHT:
+ ret = s->dc_panel_fb_height;
+ break;
+ case SM501_DC_PANEL_TL_LOC:
+ ret = s->dc_panel_tl_location;
+ break;
+ case SM501_DC_PANEL_BR_LOC:
+ ret = s->dc_panel_br_location;
+ break;
+
+ case SM501_DC_PANEL_H_TOT:
+ ret = s->dc_panel_h_total;
+ break;
+ case SM501_DC_PANEL_H_SYNC:
+ ret = s->dc_panel_h_sync;
+ break;
+ case SM501_DC_PANEL_V_TOT:
+ ret = s->dc_panel_v_total;
+ break;
+ case SM501_DC_PANEL_V_SYNC:
+ ret = s->dc_panel_v_sync;
+ break;
+
+ case SM501_DC_CRT_CONTROL:
+ ret = s->dc_crt_control;
+ break;
+ case SM501_DC_CRT_FB_ADDR:
+ ret = s->dc_crt_fb_addr;
+ break;
+ case SM501_DC_CRT_FB_OFFSET:
+ ret = s->dc_crt_fb_offset;
+ break;
+ case SM501_DC_CRT_H_TOT:
+ ret = s->dc_crt_h_total;
+ break;
+ case SM501_DC_CRT_H_SYNC:
+ ret = s->dc_crt_h_sync;
+ break;
+ case SM501_DC_CRT_V_TOT:
+ ret = s->dc_crt_v_total;
+ break;
+ case SM501_DC_CRT_V_SYNC:
+ ret = s->dc_crt_v_sync;
+ break;
+
+ case SM501_DC_CRT_HWC_ADDR:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC_CRT_HWC_LOC:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_1_2:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_3:
+ ret = s->dc_crt_hwc_addr;
+ break;
+
+ default:
+ printf("sm501 disp ctrl : not implemented register read."
+ " addr=%x, offset=%x\n", addr, offset);
+ assert(0);
+ }
+
+ return ret;
+}
+
+static void sm501_disp_ctrl_write(void *opaque,
+ target_phys_addr_t addr,
+ uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
+ SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, ofs=%x, val=%x\n",
+ addr, offset, value);
+
+ switch(offset) {
+ case SM501_DC_PANEL_CONTROL:
+ s->dc_panel_control = value & 0x0FFF73FF;
+ break;
+ case SM501_DC_PANEL_PANNING_CONTROL:
+ s->dc_panel_panning_control = value & 0xFF3FFF3F;
+ break;
+ case SM501_DC_PANEL_FB_ADDR:
+ s->dc_panel_fb_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_PANEL_FB_OFFSET:
+ s->dc_panel_fb_offset = value & 0x3FF03FF0;
+ break;
+ case SM501_DC_PANEL_FB_WIDTH:
+ s->dc_panel_fb_width = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_FB_HEIGHT:
+ s->dc_panel_fb_height = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_TL_LOC:
+ s->dc_panel_tl_location = value & 0x07FF07FF;
+ break;
+ case SM501_DC_PANEL_BR_LOC:
+ s->dc_panel_br_location = value & 0x07FF07FF;
+ break;
+
+ case SM501_DC_PANEL_H_TOT:
+ s->dc_panel_h_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_H_SYNC:
+ s->dc_panel_h_sync = value & 0x00FF0FFF;
+ break;
+ case SM501_DC_PANEL_V_TOT:
+ s->dc_panel_v_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_V_SYNC:
+ s->dc_panel_v_sync = value & 0x003F0FFF;
+ break;
+
+ case SM501_DC_PANEL_HWC_ADDR:
+ s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_PANEL_HWC_LOC:
+ s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_HWC_COLOR_1_2:
+ s->dc_panel_hwc_addr = value;
+ break;
+ case SM501_DC_PANEL_HWC_COLOR_3:
+ s->dc_panel_hwc_addr = value & 0x0000FFFF;
+ break;
+
+ case SM501_DC_CRT_CONTROL:
+ s->dc_crt_control = value & 0x0003FFFF;
+ break;
+ case SM501_DC_CRT_FB_ADDR:
+ s->dc_crt_fb_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_CRT_FB_OFFSET:
+ s->dc_crt_fb_offset = value & 0x3FF03FF0;
+ break;
+ case SM501_DC_CRT_H_TOT:
+ s->dc_crt_h_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_CRT_H_SYNC:
+ s->dc_crt_h_sync = value & 0x00FF0FFF;
+ break;
+ case SM501_DC_CRT_V_TOT:
+ s->dc_crt_v_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_CRT_V_SYNC:
+ s->dc_crt_v_sync = value & 0x003F0FFF;
+ break;
+
+ case SM501_DC_CRT_HWC_ADDR:
+ s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_CRT_HWC_LOC:
+ s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_1_2:
+ s->dc_crt_hwc_addr = value;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_3:
+ s->dc_crt_hwc_addr = value & 0x0000FFFF;
+ break;
+
+ default:
+ printf("sm501 disp ctrl : not implemented register write."
+ " addr=%x, val=%x\n", addr, value);
+ assert(0);
+ }
+}
+
+static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
+ NULL,
+ NULL,
+ &sm501_disp_ctrl_read,
+};
+
+static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
+ NULL,
+ NULL,
+ &sm501_disp_ctrl_write,
+};
+
+static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
+ + SM501_DC + SM501_DC_PANEL_PALETTE);
+ SM501_DPRINTF("sm501 palette read addr=%x, offset=%x\n", addr, offset);
+
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+
+ assert(0 <= offset && offset < 0x400 * 3);
+ return *(uint32_t*)&s->dc_palette[offset];
+}
+
+static void sm501_palette_write(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
+ + SM501_DC + SM501_DC_PANEL_PALETTE);
+ SM501_DPRINTF("sm501 palette write addr=%x, ofs=%x, val=%x\n",
+ addr, offset, value);
+
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+
+ assert(0 <= offset && offset < 0x400 * 3);
+ *(uint32_t*)&s->dc_palette[offset] = value;
+}
+
+static CPUReadMemoryFunc *sm501_palette_readfn[] = {
+ &sm501_palette_read,
+ &sm501_palette_read,
+ &sm501_palette_read,
+};
+
+static CPUWriteMemoryFunc *sm501_palette_writefn[] = {
+ &sm501_palette_write,
+ &sm501_palette_write,
+ &sm501_palette_write,
+};
+
+#if !defined(USE_NORMAL_RAM)
+
+static uint32_t sm501_lm_read(void *opaque, target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - s->base;
+ return *(uint32_t*)&s->local_mem[offset];
+}
+
+static uint32_t sm501_lm_readb(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_lm_read(opaque, addr);
+}
+
+static uint32_t sm501_lm_readw(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_lm_read(opaque, addr);
+}
+
+static uint32_t sm501_lm_readl(void *opaque, target_phys_addr_t addr)
+{
+ return sm501_lm_read(opaque, addr);
+}
+
+static void sm501_lm_write(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - s->base;
+ *(uint32_t*)&s->local_mem[offset] = value;
+}
+
+static void sm501_lm_writeb(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_lm_write(opaque, addr, value);
+}
+
+static void sm501_lm_writew(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_lm_write(opaque, addr, value);
+}
+
+static void sm501_lm_writel(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ sm501_lm_write(opaque, addr, value);
+}
+
+static CPUReadMemoryFunc *sm501_lm_readfn[] = {
+ &sm501_lm_readb,
+ &sm501_lm_readw,
+ &sm501_lm_readl,
+};
+
+static CPUWriteMemoryFunc *sm501_lm_writefn[] = {
+ &sm501_lm_writeb,
+ &sm501_lm_writew,
+ &sm501_lm_writel,
+};
+
+#endif
+
+/* draw line functions for all console modes */
+
+#include "pixel_ops.h"
+
+typedef void draw_line_func(uint8_t *d, const uint8_t *s,
+ int width, const uint32_t *pal);
+
+#define DEPTH 8
+#include "sm501_template.h"
+
+#define DEPTH 15
+#include "sm501_template.h"
+
+#define BGR_FORMAT
+#define DEPTH 15
+#include "sm501_template.h"
+
+#define DEPTH 16
+#include "sm501_template.h"
+
+#define BGR_FORMAT
+#define DEPTH 16
+#include "sm501_template.h"
+
+#define DEPTH 32
+#include "sm501_template.h"
+
+#define BGR_FORMAT
+#define DEPTH 32
+#include "sm501_template.h"
+
+static draw_line_func * draw_line8_funcs[] = {
+ draw_line8_8,
+ draw_line8_15,
+ draw_line8_16,
+ draw_line8_32,
+ draw_line8_32bgr,
+ draw_line8_15bgr,
+ draw_line8_16bgr,
+};
+
+static draw_line_func * draw_line16_funcs[] = {
+ draw_line16_8,
+ draw_line16_15,
+ draw_line16_16,
+ draw_line16_32,
+ draw_line16_32bgr,
+ draw_line16_15bgr,
+ draw_line16_16bgr,
+};
+
+static draw_line_func * draw_line32_funcs[] = {
+ draw_line32_8,
+ draw_line32_15,
+ draw_line32_16,
+ draw_line32_32,
+ draw_line32_32bgr,
+ draw_line32_15bgr,
+ draw_line32_16bgr,
+};
+
+static inline int get_depth_index(DisplayState *s)
+{
+ switch(s->depth) {
+ default:
+ case 8:
+ return 0;
+ case 15:
+ if (s->bgr)
+ return 5;
+ else
+ return 1;
+ case 16:
+ if (s->bgr)
+ return 6;
+ else
+ return 2;
+ case 32:
+ if (s->bgr)
+ return 4;
+ else
+ return 3;
+ }
+}
+
+static void sm501_draw_crt(SM501State * s)
+{
+ int y;
+ int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
+ int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
+
+ uint8_t * src = s->local_mem;
+ int src_bpp = 0;
+ uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
+ - SM501_DC_PANEL_PALETTE];
+ int ds_depth_index = get_depth_index(s->ds);
+ draw_line_func * draw_line = NULL;
+
+ switch (s->dc_crt_control & 3) {
+ case SM501_DC_CRT_CONTROL_8BPP:
+ src_bpp = 1;
+ draw_line = draw_line8_funcs[ds_depth_index];
+ break;
+ case SM501_DC_CRT_CONTROL_16BPP:
+ src_bpp = 2;
+ draw_line = draw_line16_funcs[ds_depth_index];
+ break;
+ case SM501_DC_CRT_CONTROL_32BPP:
+ src_bpp = 4;
+ draw_line = draw_line32_funcs[ds_depth_index];
+ break;
+ }
+
+ /* adjust console size */
+ if (s->last_width != width || s->last_height != height) {
+ qemu_console_resize(s->console, width, height);
+ s->last_width = width;
+ s->last_height = height;
+ }
+
+ /* TODO : check VRAM dirty flag and update partialy */
+
+ /* full screen update */
+ for (y = 0; y < height; y++) {
+#if !defined(USE_NORMAL_RAM)
+ /* TODO : implement draw_line using normal RAM & VGA_DIRTY_FLAG */
+ draw_line(&s->ds->data[y * width * 4], src, width, palette);
+#endif
+ src += width * src_bpp;
+ }
+
+ dpy_update(s->ds, 0, 0, width, height);
+}
+
+static void sm501_update_display(void *opaque)
+{
+ SM501State * s = (SM501State *)opaque;
+
+ if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
+ sm501_draw_crt(s);
+}
+
+void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
+ uint32_t local_mem_bytes, CharDriverState *chr)
+{
+ SM501State * s;
+#if !defined(USE_NORMAL_RAM)
+ int sm501_lm_index;
+#endif
+ int sm501_system_config_index;
+ int sm501_disp_ctrl_index;
+ int sm501_palette_index;
+
+ /* allocate management data region */
+ s = (SM501State *)qemu_mallocz(sizeof(SM501State));
+ s->base = base;
+ s->local_mem_size_index
+ = get_local_mem_size_index(local_mem_bytes);
+ SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
+ s->local_mem_size_index);
+ s->system_control = 0x00100000;
+ s->misc_control = 0x00001000; /* assumes SH, active=low */
+ s->dc_panel_control = 0x00010000;
+ s->dc_crt_control = 0x00010000;
+ s->ds = ds;
+
+ /* allocate local memory */
+ /* TODO : Allocate VRAM as normal RAM with local_mem_base.*/
+#ifdef USE_NORMAL_RAM
+ cpu_register_physical_memory(base, local_mem_bytes, local_mem_base);
+#else
+ s->local_mem = qemu_mallocz(get_local_mem_size(s));
+ sm501_lm_index = cpu_register_io_memory(0, sm501_lm_readfn,
+ sm501_lm_writefn, s);
+ cpu_register_physical_memory(base, get_local_mem_size(s), sm501_lm_index);
+#endif
+
+ /* map mmio */
+ sm501_system_config_index
+ = cpu_register_io_memory(0, sm501_system_config_readfn,
+ sm501_system_config_writefn, s);
+ cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
+ 0x6c, sm501_system_config_index);
+ sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn,
+ sm501_disp_ctrl_writefn, s);
+ cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
+ 0x400, sm501_disp_ctrl_index);
+
+ sm501_palette_index = cpu_register_io_memory(0, sm501_palette_readfn,
+ sm501_palette_writefn, s);
+ cpu_register_physical_memory(base + MMIO_BASE_OFFSET
+ + SM501_DC + SM501_DC_PANEL_PALETTE,
+ 0x400 * 3, sm501_palette_index);
+
+ /* bridge to serial emulation module */
+ if (chr)
+ serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
+ 0, /* TODO : chain irq to IRL */
+ 115200, chr, 1);
+
+ /* create qemu graphic console */
+ s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
+ NULL, NULL, s);
+}
Index: trunk/hw/sm501_template.h
===================================================================
--- trunk/hw/sm501_template.h (revision 0)
+++ trunk/hw/sm501_template.h (revision 0)
@@ -0,0 +1,99 @@
+/*
+ * Pixel drawing function templates for QEMU SM501 Device
+ *
+ * Copyright (c) 2008 Shin-ichiro KAWASAKI
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if DEPTH == 8
+#define BPP 1
+#define PIXEL_TYPE uint8_t
+#elif DEPTH == 15 || DEPTH == 16
+#define BPP 2
+#define PIXEL_TYPE uint16_t
+#elif DEPTH == 32
+#define BPP 4
+#define PIXEL_TYPE uint32_t
+#else
+#error unsupport depth
+#endif
+
+#ifdef BGR_FORMAT
+#define PIXEL_NAME glue(DEPTH, bgr)
+#else
+#define PIXEL_NAME DEPTH
+#endif /* BGR_FORMAT */
+
+
+static void glue(draw_line8_, PIXEL_NAME)(
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+{
+ uint8_t v, r, g, b;
+ do {
+ v = *s;
+ r = (pal[v] >> 16) & 0xff;
+ g = (pal[v] >> 8) & 0xff;
+ b = (pal[v] >> 0) & 0xff;
+ ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s ++;
+ d += BPP;
+ } while (-- width != 0);
+}
+
+static void glue(draw_line16_, PIXEL_NAME)(
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+{
+ uint16_t rgb565;
+ uint8_t r, g, b;
+
+ do {
+ rgb565 = *(uint16_t*)s;
+ r = ((rgb565 >> 11) & 0x1f) << 3;
+ g = ((rgb565 >> 5) & 0x3f) << 2;
+ b = ((rgb565 >> 0) & 0x1f) << 3;
+ ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s += 2;
+ d += BPP;
+ } while (-- width != 0);
+}
+
+static void glue(draw_line32_, PIXEL_NAME)(
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+{
+ uint32_t argb8888;
+ uint8_t r, g, b;
+
+ do {
+ argb8888 = *(uint32_t*)s;
+ r = (argb8888 >> 16) & 0xff;
+ g = (argb8888 >> 8) & 0xff;
+ b = (argb8888 >> 0) & 0xff;
+ ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s += 4;
+ d += BPP;
+ } while (-- width != 0);
+}
+
+#undef DEPTH
+#undef BPP
+#undef PIXEL_TYPE
+#undef PIXEL_NAME
+#undef BGR_FORMAT
+
Index: trunk/hw/devices.h
===================================================================
--- trunk/hw/devices.h (revision 5594)
+++ trunk/hw/devices.h (working copy)
@@ -71,4 +71,7 @@
qemu_irq handler);
qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
+/* sm501.c */
+void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
+ uint32_t local_mem_bytes, CharDriverState *chr);
#endif
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] When should I use qemu_ram_alloc(), and how?
2008-11-02 6:52 ` Blue Swirl
2008-11-04 15:10 ` Shin-ichiro KAWASAKI
@ 2008-11-04 15:27 ` takasi-y
2008-11-04 19:14 ` [Qemu-devel] " Blue Swirl
1 sibling, 1 reply; 14+ messages in thread
From: takasi-y @ 2008-11-04 15:27 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
Hi,
# Reusing thread, to video memory allocation related question.
Could you please give me answer to my question ?
Attached diff is for adding cirrus_vga onto r2d, for explanatin.
The point is here.
- cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
+ r = qemu_ram_alloc(SDRAM_SIZE);
+ cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, r);
Apparently, r2d had not used qemu_ram_alloc() (it is working, though).
I added it here without knowing well about qemu memory system
(this one is working fine, too).
Maybe, allocation is needed always(even when without VGA), isn't it?
Are there any restriction between alloced address and register address?
I am worried about it because PC seems to make them equal.
Cheers,
/yoshii
# This patch is not for being merged to the repository.
SH: r2d Add cirrus_vga support.
r2d doesn't have cirrus VGA on board, imagine it is in PCI slot.
I have to reduce cirrus_vga PCI memory window size 32M to 8M,
because SH has only 16MB linear space for PCI.
Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
---
Makefile.target | 2 +-
hw/cirrus_vga.c | 2 +-
hw/r2d.c | 9 +++++++--
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/Makefile.target b/Makefile.target
index dedb944..36f1273 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -726,7 +726,7 @@ endif
ifeq ($(TARGET_BASE_ARCH), sh4)
OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sh_pci.o
-OBJS+= ide.o
+OBJS+= ide.o vga.o cirrus_vga.o
endif
ifeq ($(TARGET_BASE_ARCH), m68k)
OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index af9c9e6..286dfe1 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -3311,7 +3311,7 @@ void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
/* memory #0 LFB */
/* memory #1 memory-mapped I/O */
/* XXX: s->vram_size must be a power of two */
- pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
+ pci_register_io_region((PCIDevice *)d, 0, vga_ram_size,
PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
if (device_id == CIRRUS_ID_CLGD5446) {
pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
diff --git a/hw/r2d.c b/hw/r2d.c
index 54529ca..c1f7e92 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -207,6 +207,7 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
qemu_irq *irq;
PCIBus *pci;
int i;
+ ram_addr_t r;
if (!cpu_model)
cpu_model = "SH7751R";
@@ -218,11 +219,15 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
}
/* Allocate memory space */
- cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
+ r = qemu_ram_alloc(SDRAM_SIZE);
+ cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, r);
/* Register peripherals */
s = sh7750_init(env);
irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
+ /* VGA : Just after SDRAM in memory space. Top in PCI space. */
+ r = qemu_ram_alloc(vga_ram_size);
+ pci_cirrus_vga_init(pci, ds, phys_ram_base + r, r, vga_ram_size);
/* onboard CF (True IDE mode, Master only). */
mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
@@ -256,5 +261,5 @@ QEMUMachine r2d_machine = {
.name = "r2d",
.desc = "r2d-plus board",
.init = r2d_init,
- .ram_require = SDRAM_SIZE | RAMSIZE_FIXED,
+ .ram_require = (SDRAM_SIZE + 8*1024*1024) | RAMSIZE_FIXED,
};
--
1.5.6.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4
2008-11-04 15:10 ` Shin-ichiro KAWASAKI
@ 2008-11-04 19:11 ` Blue Swirl
2008-11-05 17:09 ` [Qemu-devel] [PATCH] [RESEND] " Shin-ichiro KAWASAKI
0 siblings, 1 reply; 14+ messages in thread
From: Blue Swirl @ 2008-11-04 19:11 UTC (permalink / raw)
To: qemu-devel
On 11/4/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> Thank you for reviewing!
>
> I add the new version of patch to this mail, which reflects
> you and andrzej's comments. Some more comments on it will be
> appreciated. Especially advice on VRAM implementation with
> normal RAM will be useful for me.
> > The display buffer should be allocated using machine definition
> .ram_require.
> >
>
> I tried normal RAM implementation : "#define USE_NORMAL_RAM" in the patch
> will
> turn the new implementation on. But it causes system hang during SH-Linux
> boot up.
> The initial VRAM clearance seems to cause the hang.
> The reason might be my wrong implementation, or any MMU problem of SH4.
>
> I did,
> - added VRAM size to .ram_require
> - invoked qemu_ram_alloc() with the VRAM size parameter,
> - and invoked cpu_register_physical_memory(), passing the
> return value of
> qemu_ram_alloc() as third parameter.
>
> Is this sequence correct?
Yes, but the system RAM is not allocated using qemu_ram_alloc. Now
qemu_ram_alloc gives the same area (0 to VRAM_SIZE) the second time.
So the following:
/* Allocate memory space */
cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
should be changed to:
ram_addr = qemu_ram_alloc(SDRAM_SIZE);
cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, ram_addr);
Maybe that helps?
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] Re: When should I use qemu_ram_alloc(), and how?
2008-11-04 15:27 ` [Qemu-devel] When should I use qemu_ram_alloc(), and how? takasi-y
@ 2008-11-04 19:14 ` Blue Swirl
2008-11-04 19:32 ` Anthony Liguori
2008-11-05 13:29 ` takasi-y
0 siblings, 2 replies; 14+ messages in thread
From: Blue Swirl @ 2008-11-04 19:14 UTC (permalink / raw)
To: takasi-y@ops.dti.ne.jp; +Cc: qemu-devel
On 11/4/08, takasi-y@ops.dti.ne.jp <takasi-y@ops.dti.ne.jp> wrote:
> Hi,
> # Reusing thread, to video memory allocation related question.
> Could you please give me answer to my question ?
>
> Attached diff is for adding cirrus_vga onto r2d, for explanatin.
> The point is here.
> - cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
> + r = qemu_ram_alloc(SDRAM_SIZE);
> + cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, r);
Well, I haven't been using qemu_ram_alloc on Sparc but instead used
direct offsets. Maybe I should convert. Also, all ram allocation
should be done using qemu_ram_alloc (especially system RAM), not just
some devices.
> Apparently, r2d had not used qemu_ram_alloc() (it is working, though).
> I added it here without knowing well about qemu memory system
> (this one is working fine, too).
>
> Maybe, allocation is needed always(even when without VGA), isn't it?
I don't think so, unallocated memory will be just unused.
> Are there any restriction between alloced address and register address?
> I am worried about it because PC seems to make them equal.
There are some code that assumes that CPU address for RAM can be
converted to host address using phys_ram_base + CPU address.
> - pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
> + pci_register_io_region((PCIDevice *)d, 0, vga_ram_size,
To me this change looks OK, but I think it should be separate and the
PC folks should consider if it breaks something.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] Re: When should I use qemu_ram_alloc(), and how?
2008-11-04 19:14 ` [Qemu-devel] " Blue Swirl
@ 2008-11-04 19:32 ` Anthony Liguori
2008-11-05 13:29 ` takasi-y
1 sibling, 0 replies; 14+ messages in thread
From: Anthony Liguori @ 2008-11-04 19:32 UTC (permalink / raw)
To: qemu-devel; +Cc: takasi-y@ops.dti.ne.jp
Blue Swirl wrote:
> On 11/4/08, takasi-y@ops.dti.ne.jp <takasi-y@ops.dti.ne.jp> wrote:
>
>
>> - pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
>> + pci_register_io_region((PCIDevice *)d, 0, vga_ram_size,
No, I think this is wrong. The PCI IO region is independent of
vga_ram_size.
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] Re: When should I use qemu_ram_alloc(), and how?
2008-11-04 19:14 ` [Qemu-devel] " Blue Swirl
2008-11-04 19:32 ` Anthony Liguori
@ 2008-11-05 13:29 ` takasi-y
1 sibling, 0 replies; 14+ messages in thread
From: takasi-y @ 2008-11-05 13:29 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
Thank you!
> Well, I haven't been using qemu_ram_alloc on Sparc but instead used
> direct offsets. Maybe I should convert. Also, all ram allocation
> should be done using qemu_ram_alloc (especially system RAM), not just
> some devices.
I come to know why yours and my case worked fine even without using
qemu_ram_alloc(). What important was offset(phys_ram_alloc_offset).
Anyway I will use qemu_ram_alloc() to maintain the offset.
> > Maybe, allocation is needed always(even when without VGA), isn't it?
>
> I don't think so, unallocated memory will be just unused.
>
> > Are there any restriction between alloced address and register address?
> > I am worried about it because PC seems to make them equal.
>
> There are some code that assumes that CPU address for RAM can be
> converted to host address using phys_ram_base + CPU address.
Ah, finally I came to know what a comment at allocating BIOS in pc.c says.
It means that When memory layout is like "32M(ROM)+32M(blank)+64M(RAM)"
I have to allocate 32M blank(without registering) to keep offset between
host and (emulated)CPU address consistent.
> > - pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
> > + pci_register_io_region((PCIDevice *)d, 0, vga_ram_size,
>
> To me this change looks OK, but I think it should be separate and the
> PC folks should consider if it breaks something.
Ah, sorry. I have attached the patch to aid explanation. But I think it
can not be merged into main repository. (Unfortunately?) real cirrus VGA
claims 32M memory regardless with VRAM size. So, if I modified the
code, it will be an emulation of something not really exists.
/yoshii
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH] [RESEND] SM501 emulation for R2D-SH4
2008-11-04 19:11 ` Blue Swirl
@ 2008-11-05 17:09 ` Shin-ichiro KAWASAKI
2008-11-05 18:25 ` Blue Swirl
0 siblings, 1 reply; 14+ messages in thread
From: Shin-ichiro KAWASAKI @ 2008-11-05 17:09 UTC (permalink / raw)
To: qemu-devel
Blue Swirl wrote:
> On 11/4/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
>> Thank you for reviewing!
>>
>> I add the new version of patch to this mail, which reflects
>> you and andrzej's comments. Some more comments on it will be
>> appreciated. Especially advice on VRAM implementation with
>> normal RAM will be useful for me.
>>> The display buffer should be allocated using machine definition
>> .ram_require.
>> I tried normal RAM implementation : "#define USE_NORMAL_RAM" in the patch
>> will
>> turn the new implementation on. But it causes system hang during SH-Linux
>> boot up.
>> The initial VRAM clearance seems to cause the hang.
>> The reason might be my wrong implementation, or any MMU problem of SH4.
>>
>> I did,
>> - added VRAM size to .ram_require
>> - invoked qemu_ram_alloc() with the VRAM size parameter,
>> - and invoked cpu_register_physical_memory(), passing the
>> return value of
>> qemu_ram_alloc() as third parameter.
>>
>> Is this sequence correct?
>
> Yes, but the system RAM is not allocated using qemu_ram_alloc. Now
> qemu_ram_alloc gives the same area (0 to VRAM_SIZE) the second time.
>
> So the following:
> /* Allocate memory space */
> cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
> should be changed to:
> ram_addr = qemu_ram_alloc(SDRAM_SIZE);
> cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, ram_addr);
>
> Maybe that helps?
Yes, it helps. Thank you!
Here's the new patch which uses normal RAM as the VRAM, and
checks VGA_DIRTY_FLAG for partial update.
I think it is ready for merge to the trunk.
Could anyone help it?
Regards,
Shin-ichiro KAWASAKI
Signed-off-by: Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp>
Index: trunk/Makefile.target
===================================================================
--- trunk/Makefile.target (revision 5594)
+++ trunk/Makefile.target (working copy)
@@ -725,7 +725,7 @@
endif
ifeq ($(TARGET_BASE_ARCH), sh4)
OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
-OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o
+OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o serial.o
endif
ifeq ($(TARGET_BASE_ARCH), m68k)
OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
Index: trunk/hw/r2d.c
===================================================================
--- trunk/hw/r2d.c (revision 5594)
+++ trunk/hw/r2d.c (working copy)
@@ -25,12 +25,15 @@
#include "hw.h"
#include "sh.h"
+#include "devices.h"
#include "sysemu.h"
#include "boards.h"
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000
+#define SM501_VRAM_SIZE 0x800000
+
#define PA_POWOFF 0x30
#define PA_VERREG 0x32
#define PA_OUTPORT 0x36
@@ -133,6 +136,7 @@
{
CPUState *env;
struct SH7750State *s;
+ ram_addr_t sdram_addr, sm501_vga_ram_addr;
if (!cpu_model)
cpu_model = "SH7751R";
@@ -144,10 +148,14 @@
}
/* Allocate memory space */
- cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
+ sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
+ cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
/* Register peripherals */
r2d_fpga_init(0x04000000);
s = sh7750_init(env);
+ sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
+ sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
+ serial_hds[2]);
/* Todo: register on board registers */
{
int kernel_size;
@@ -167,5 +175,5 @@
.name = "r2d",
.desc = "r2d-plus board",
.init = r2d_init,
- .ram_require = SDRAM_SIZE | RAMSIZE_FIXED,
+ .ram_require = (SDRAM_SIZE + SM501_VRAM_SIZE) | RAMSIZE_FIXED,
};
Index: trunk/hw/sm501.c
===================================================================
--- trunk/hw/sm501.c (revision 0)
+++ trunk/hw/sm501.c (revision 0)
@@ -0,0 +1,1129 @@
+/*
+ * QEMU SM501 Device
+ *
+ * Copyright (c) 2008 Shin-ichiro KAWASAKI
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <assert.h>
+#include "hw.h"
+#include "pc.h"
+#include "console.h"
+
+/*
+ * Status: 2008/11/02
+ * - Minimum implementation for Linux console : mmio regs and CRT layer.
+ * - Always updates full screen.
+ *
+ * TODO:
+ * - Panel support
+ * - Hardware cursor support
+ * - Touch panel support
+ * - USB support
+ * - UART support
+ * - Performance tuning
+ */
+
+//#define DEBUG_SM501
+//#define DEBUG_BITBLT
+
+#ifdef DEBUG_SM501
+#define SM501_DPRINTF(fmt...) printf(fmt)
+#else
+#define SM501_DPRINTF(fmt...) do {} while(0)
+#endif
+
+
+#define MMIO_BASE_OFFSET 0x3e00000
+
+/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
+
+/* System Configuration area */
+/* System config base */
+#define SM501_SYS_CONFIG (0x000000)
+
+/* config 1 */
+#define SM501_SYSTEM_CONTROL (0x000000)
+
+#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
+#define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
+#define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
+
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
+
+#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
+#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
+#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
+#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
+
+/* miscellaneous control */
+
+#define SM501_MISC_CONTROL (0x000004)
+
+#define SM501_MISC_BUS_SH (0x0)
+#define SM501_MISC_BUS_PCI (0x1)
+#define SM501_MISC_BUS_XSCALE (0x2)
+#define SM501_MISC_BUS_NEC (0x6)
+#define SM501_MISC_BUS_MASK (0x7)
+
+#define SM501_MISC_VR_62MB (1<<3)
+#define SM501_MISC_CDR_RESET (1<<7)
+#define SM501_MISC_USB_LB (1<<8)
+#define SM501_MISC_USB_SLAVE (1<<9)
+#define SM501_MISC_BL_1 (1<<10)
+#define SM501_MISC_MC (1<<11)
+#define SM501_MISC_DAC_POWER (1<<12)
+#define SM501_MISC_IRQ_INVERT (1<<16)
+#define SM501_MISC_SH (1<<17)
+
+#define SM501_MISC_HOLD_EMPTY (0<<18)
+#define SM501_MISC_HOLD_8 (1<<18)
+#define SM501_MISC_HOLD_16 (2<<18)
+#define SM501_MISC_HOLD_24 (3<<18)
+#define SM501_MISC_HOLD_32 (4<<18)
+#define SM501_MISC_HOLD_MASK (7<<18)
+
+#define SM501_MISC_FREQ_12 (1<<24)
+#define SM501_MISC_PNL_24BIT (1<<25)
+#define SM501_MISC_8051_LE (1<<26)
+
+
+
+#define SM501_GPIO31_0_CONTROL (0x000008)
+#define SM501_GPIO63_32_CONTROL (0x00000C)
+#define SM501_DRAM_CONTROL (0x000010)
+
+/* command list */
+#define SM501_ARBTRTN_CONTROL (0x000014)
+
+/* command list */
+#define SM501_COMMAND_LIST_STATUS (0x000024)
+
+/* interrupt debug */
+#define SM501_RAW_IRQ_STATUS (0x000028)
+#define SM501_RAW_IRQ_CLEAR (0x000028)
+#define SM501_IRQ_STATUS (0x00002C)
+#define SM501_IRQ_MASK (0x000030)
+#define SM501_DEBUG_CONTROL (0x000034)
+
+/* power management */
+#define SM501_POWERMODE_P2X_SRC (1<<29)
+#define SM501_POWERMODE_V2X_SRC (1<<20)
+#define SM501_POWERMODE_M_SRC (1<<12)
+#define SM501_POWERMODE_M1_SRC (1<<4)
+
+#define SM501_CURRENT_GATE (0x000038)
+#define SM501_CURRENT_CLOCK (0x00003C)
+#define SM501_POWER_MODE_0_GATE (0x000040)
+#define SM501_POWER_MODE_0_CLOCK (0x000044)
+#define SM501_POWER_MODE_1_GATE (0x000048)
+#define SM501_POWER_MODE_1_CLOCK (0x00004C)
+#define SM501_SLEEP_MODE_GATE (0x000050)
+#define SM501_POWER_MODE_CONTROL (0x000054)
+
+/* power gates for units within the 501 */
+#define SM501_GATE_HOST (0)
+#define SM501_GATE_MEMORY (1)
+#define SM501_GATE_DISPLAY (2)
+#define SM501_GATE_2D_ENGINE (3)
+#define SM501_GATE_CSC (4)
+#define SM501_GATE_ZVPORT (5)
+#define SM501_GATE_GPIO (6)
+#define SM501_GATE_UART0 (7)
+#define SM501_GATE_UART1 (8)
+#define SM501_GATE_SSP (10)
+#define SM501_GATE_USB_HOST (11)
+#define SM501_GATE_USB_GADGET (12)
+#define SM501_GATE_UCONTROLLER (17)
+#define SM501_GATE_AC97 (18)
+
+/* panel clock */
+#define SM501_CLOCK_P2XCLK (24)
+/* crt clock */
+#define SM501_CLOCK_V2XCLK (16)
+/* main clock */
+#define SM501_CLOCK_MCLK (8)
+/* SDRAM controller clock */
+#define SM501_CLOCK_M1XCLK (0)
+
+/* config 2 */
+#define SM501_PCI_MASTER_BASE (0x000058)
+#define SM501_ENDIAN_CONTROL (0x00005C)
+#define SM501_DEVICEID (0x000060)
+/* 0x050100A0 */
+
+#define SM501_DEVICEID_SM501 (0x05010000)
+#define SM501_DEVICEID_IDMASK (0xffff0000)
+#define SM501_DEVICEID_REVMASK (0x000000ff)
+
+#define SM501_PLLCLOCK_COUNT (0x000064)
+#define SM501_MISC_TIMING (0x000068)
+#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
+
+#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
+
+/* GPIO base */
+#define SM501_GPIO (0x010000)
+#define SM501_GPIO_DATA_LOW (0x00)
+#define SM501_GPIO_DATA_HIGH (0x04)
+#define SM501_GPIO_DDR_LOW (0x08)
+#define SM501_GPIO_DDR_HIGH (0x0C)
+#define SM501_GPIO_IRQ_SETUP (0x10)
+#define SM501_GPIO_IRQ_STATUS (0x14)
+#define SM501_GPIO_IRQ_RESET (0x14)
+
+/* I2C controller base */
+#define SM501_I2C (0x010040)
+#define SM501_I2C_BYTE_COUNT (0x00)
+#define SM501_I2C_CONTROL (0x01)
+#define SM501_I2C_STATUS (0x02)
+#define SM501_I2C_RESET (0x02)
+#define SM501_I2C_SLAVE_ADDRESS (0x03)
+#define SM501_I2C_DATA (0x04)
+
+/* SSP base */
+#define SM501_SSP (0x020000)
+
+/* Uart 0 base */
+#define SM501_UART0 (0x030000)
+
+/* Uart 1 base */
+#define SM501_UART1 (0x030020)
+
+/* USB host port base */
+#define SM501_USB_HOST (0x040000)
+
+/* USB slave/gadget base */
+#define SM501_USB_GADGET (0x060000)
+
+/* USB slave/gadget data port base */
+#define SM501_USB_GADGET_DATA (0x070000)
+
+/* Display controller/video engine base */
+#define SM501_DC (0x080000)
+
+/* common defines for the SM501 address registers */
+#define SM501_ADDR_FLIP (1<<31)
+#define SM501_ADDR_EXT (1<<27)
+#define SM501_ADDR_CS1 (1<<26)
+#define SM501_ADDR_MASK (0x3f << 26)
+
+#define SM501_FIFO_MASK (0x3 << 16)
+#define SM501_FIFO_1 (0x0 << 16)
+#define SM501_FIFO_3 (0x1 << 16)
+#define SM501_FIFO_7 (0x2 << 16)
+#define SM501_FIFO_11 (0x3 << 16)
+
+/* common registers for panel and the crt */
+#define SM501_OFF_DC_H_TOT (0x000)
+#define SM501_OFF_DC_V_TOT (0x008)
+#define SM501_OFF_DC_H_SYNC (0x004)
+#define SM501_OFF_DC_V_SYNC (0x00C)
+
+#define SM501_DC_PANEL_CONTROL (0x000)
+
+#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
+#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
+#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
+#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
+#define SM501_DC_PANEL_CONTROL_DP (1<<23)
+
+#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
+#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
+
+#define SM501_DC_PANEL_CONTROL_DE (1<<20)
+
+#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
+
+#define SM501_DC_PANEL_CONTROL_CP (1<<14)
+#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
+#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
+#define SM501_DC_PANEL_CONTROL_CK (1<<9)
+#define SM501_DC_PANEL_CONTROL_TE (1<<8)
+#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
+#define SM501_DC_PANEL_CONTROL_VP (1<<6)
+#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
+#define SM501_DC_PANEL_CONTROL_HP (1<<4)
+#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
+#define SM501_DC_PANEL_CONTROL_EN (1<<2)
+
+#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
+#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
+#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
+
+
+#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
+#define SM501_DC_PANEL_COLOR_KEY (0x008)
+#define SM501_DC_PANEL_FB_ADDR (0x00C)
+#define SM501_DC_PANEL_FB_OFFSET (0x010)
+#define SM501_DC_PANEL_FB_WIDTH (0x014)
+#define SM501_DC_PANEL_FB_HEIGHT (0x018)
+#define SM501_DC_PANEL_TL_LOC (0x01C)
+#define SM501_DC_PANEL_BR_LOC (0x020)
+#define SM501_DC_PANEL_H_TOT (0x024)
+#define SM501_DC_PANEL_H_SYNC (0x028)
+#define SM501_DC_PANEL_V_TOT (0x02C)
+#define SM501_DC_PANEL_V_SYNC (0x030)
+#define SM501_DC_PANEL_CUR_LINE (0x034)
+
+#define SM501_DC_VIDEO_CONTROL (0x040)
+#define SM501_DC_VIDEO_FB0_ADDR (0x044)
+#define SM501_DC_VIDEO_FB_WIDTH (0x048)
+#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
+#define SM501_DC_VIDEO_TL_LOC (0x050)
+#define SM501_DC_VIDEO_BR_LOC (0x054)
+#define SM501_DC_VIDEO_SCALE (0x058)
+#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
+#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
+#define SM501_DC_VIDEO_FB1_ADDR (0x064)
+#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
+
+#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
+#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
+#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
+#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
+#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
+#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
+#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
+#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
+#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
+#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
+
+#define SM501_DC_PANEL_HWC_BASE (0x0F0)
+#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
+#define SM501_DC_PANEL_HWC_LOC (0x0F4)
+#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
+#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
+
+#define SM501_HWC_EN (1<<31)
+
+#define SM501_OFF_HWC_ADDR (0x00)
+#define SM501_OFF_HWC_LOC (0x04)
+#define SM501_OFF_HWC_COLOR_1_2 (0x08)
+#define SM501_OFF_HWC_COLOR_3 (0x0C)
+
+#define SM501_DC_ALPHA_CONTROL (0x100)
+#define SM501_DC_ALPHA_FB_ADDR (0x104)
+#define SM501_DC_ALPHA_FB_OFFSET (0x108)
+#define SM501_DC_ALPHA_TL_LOC (0x10C)
+#define SM501_DC_ALPHA_BR_LOC (0x110)
+#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
+#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
+
+#define SM501_DC_CRT_CONTROL (0x200)
+
+#define SM501_DC_CRT_CONTROL_TVP (1<<15)
+#define SM501_DC_CRT_CONTROL_CP (1<<14)
+#define SM501_DC_CRT_CONTROL_VSP (1<<13)
+#define SM501_DC_CRT_CONTROL_HSP (1<<12)
+#define SM501_DC_CRT_CONTROL_VS (1<<11)
+#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
+#define SM501_DC_CRT_CONTROL_SEL (1<<9)
+#define SM501_DC_CRT_CONTROL_TE (1<<8)
+#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
+#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
+#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
+
+#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
+#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
+#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
+
+#define SM501_DC_CRT_FB_ADDR (0x204)
+#define SM501_DC_CRT_FB_OFFSET (0x208)
+#define SM501_DC_CRT_H_TOT (0x20C)
+#define SM501_DC_CRT_H_SYNC (0x210)
+#define SM501_DC_CRT_V_TOT (0x214)
+#define SM501_DC_CRT_V_SYNC (0x218)
+#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
+#define SM501_DC_CRT_CUR_LINE (0x220)
+#define SM501_DC_CRT_MONITOR_DETECT (0x224)
+
+#define SM501_DC_CRT_HWC_BASE (0x230)
+#define SM501_DC_CRT_HWC_ADDR (0x230)
+#define SM501_DC_CRT_HWC_LOC (0x234)
+#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
+#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
+
+#define SM501_DC_PANEL_PALETTE (0x400)
+
+#define SM501_DC_VIDEO_PALETTE (0x800)
+
+#define SM501_DC_CRT_PALETTE (0xC00)
+
+/* Zoom Video port base */
+#define SM501_ZVPORT (0x090000)
+
+/* AC97/I2S base */
+#define SM501_AC97 (0x0A0000)
+
+/* 8051 micro controller base */
+#define SM501_UCONTROLLER (0x0B0000)
+
+/* 8051 micro controller SRAM base */
+#define SM501_UCONTROLLER_SRAM (0x0C0000)
+
+/* DMA base */
+#define SM501_DMA (0x0D0000)
+
+/* 2d engine base */
+#define SM501_2D_ENGINE (0x100000)
+#define SM501_2D_SOURCE (0x00)
+#define SM501_2D_DESTINATION (0x04)
+#define SM501_2D_DIMENSION (0x08)
+#define SM501_2D_CONTROL (0x0C)
+#define SM501_2D_PITCH (0x10)
+#define SM501_2D_FOREGROUND (0x14)
+#define SM501_2D_BACKGROUND (0x18)
+#define SM501_2D_STRETCH (0x1C)
+#define SM501_2D_COLOR_COMPARE (0x20)
+#define SM501_2D_COLOR_COMPARE_MASK (0x24)
+#define SM501_2D_MASK (0x28)
+#define SM501_2D_CLIP_TL (0x2C)
+#define SM501_2D_CLIP_BR (0x30)
+#define SM501_2D_MONO_PATTERN_LOW (0x34)
+#define SM501_2D_MONO_PATTERN_HIGH (0x38)
+#define SM501_2D_WINDOW_WIDTH (0x3C)
+#define SM501_2D_SOURCE_BASE (0x40)
+#define SM501_2D_DESTINATION_BASE (0x44)
+#define SM501_2D_ALPHA (0x48)
+#define SM501_2D_WRAP (0x4C)
+#define SM501_2D_STATUS (0x50)
+
+#define SM501_CSC_Y_SOURCE_BASE (0xC8)
+#define SM501_CSC_CONSTANTS (0xCC)
+#define SM501_CSC_Y_SOURCE_X (0xD0)
+#define SM501_CSC_Y_SOURCE_Y (0xD4)
+#define SM501_CSC_U_SOURCE_BASE (0xD8)
+#define SM501_CSC_V_SOURCE_BASE (0xDC)
+#define SM501_CSC_SOURCE_DIMENSION (0xE0)
+#define SM501_CSC_SOURCE_PITCH (0xE4)
+#define SM501_CSC_DESTINATION (0xE8)
+#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
+#define SM501_CSC_DESTINATION_PITCH (0xF0)
+#define SM501_CSC_SCALE_FACTOR (0xF4)
+#define SM501_CSC_DESTINATION_BASE (0xF8)
+#define SM501_CSC_CONTROL (0xFC)
+
+/* 2d engine data port base */
+#define SM501_2D_ENGINE_DATA (0x110000)
+
+/* end of register definitions */
+
+
+/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
+static const uint32_t sm501_mem_local_size[] = {
+ [0] = 4*1024*1024,
+ [1] = 8*1024*1024,
+ [2] = 16*1024*1024,
+ [3] = 32*1024*1024,
+ [4] = 64*1024*1024,
+ [5] = 2*1024*1024,
+};
+#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
+
+typedef struct SM501State {
+ /* graphic console status */
+ DisplayState *ds;
+ QEMUConsole *console;
+
+ /* status & internal resources */
+ target_phys_addr_t base;
+ uint32_t local_mem_size_index;
+ uint8_t * local_mem;
+ uint32_t last_width;
+ uint32_t last_height;
+
+ /* mmio registers */
+ uint32_t system_control;
+ uint32_t misc_control;
+ uint32_t gpio_31_0_control;
+ uint32_t gpio_63_32_control;
+ uint32_t dram_control;
+ uint32_t irq_mask;
+ uint32_t misc_timing;
+ uint32_t power_mode_control;
+
+ uint32_t uart0_ier;
+ uint32_t uart0_lcr;
+ uint32_t uart0_mcr;
+ uint32_t uart0_scr;
+
+ uint8_t dc_palette[0x400 * 3];
+
+ uint32_t dc_panel_control;
+ uint32_t dc_panel_panning_control;
+ uint32_t dc_panel_fb_addr;
+ uint32_t dc_panel_fb_offset;
+ uint32_t dc_panel_fb_width;
+ uint32_t dc_panel_fb_height;
+ uint32_t dc_panel_tl_location;
+ uint32_t dc_panel_br_location;
+ uint32_t dc_panel_h_total;
+ uint32_t dc_panel_h_sync;
+ uint32_t dc_panel_v_total;
+ uint32_t dc_panel_v_sync;
+
+ uint32_t dc_panel_hwc_addr;
+ uint32_t dc_panel_hwc_location;
+ uint32_t dc_panel_hwc_color_1_2;
+ uint32_t dc_panel_hwc_color_3;
+
+ uint32_t dc_crt_control;
+ uint32_t dc_crt_fb_addr;
+ uint32_t dc_crt_fb_offset;
+ uint32_t dc_crt_h_total;
+ uint32_t dc_crt_h_sync;
+ uint32_t dc_crt_v_total;
+ uint32_t dc_crt_v_sync;
+
+ uint32_t dc_crt_hwc_addr;
+ uint32_t dc_crt_hwc_location;
+ uint32_t dc_crt_hwc_color_1_2;
+ uint32_t dc_crt_hwc_color_3;
+
+} SM501State;
+
+static uint32_t get_local_mem_size_index(uint32_t size)
+{
+ uint32_t norm_size = 0;
+ int i, index = 0;
+
+ for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) {
+ uint32_t new_size = sm501_mem_local_size[i];
+ if (new_size >= size) {
+ if (norm_size == 0 || norm_size > new_size) {
+ norm_size = new_size;
+ index = i;
+ }
+ }
+ }
+
+ return index;
+}
+
+static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
+ uint32_t ret = 0;
+ SM501_DPRINTF("sm501 system config regs : read addr=%x, offset=%x\n",
+ addr, offset);
+
+ switch(offset) {
+ case SM501_SYSTEM_CONTROL:
+ ret = s->system_control;
+ break;
+ case SM501_MISC_CONTROL:
+ ret = s->misc_control;
+ break;
+ case SM501_GPIO31_0_CONTROL:
+ ret = s->gpio_31_0_control;
+ break;
+ case SM501_GPIO63_32_CONTROL:
+ ret = s->gpio_63_32_control;
+ break;
+ case SM501_DEVICEID:
+ ret = 0x050100A0;
+ break;
+ case SM501_DRAM_CONTROL:
+ ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
+ break;
+ case SM501_IRQ_MASK:
+ ret = s->irq_mask;
+ break;
+ case SM501_MISC_TIMING:
+ /* TODO : simulate gate control */
+ ret = s->misc_timing;
+ break;
+ case SM501_CURRENT_GATE:
+ /* TODO : simulate gate control */
+ ret = 0x00021807;
+ break;
+ case SM501_CURRENT_CLOCK:
+ ret = 0x2A1A0A09;
+ break;
+ case SM501_POWER_MODE_CONTROL:
+ ret = s->power_mode_control;
+ break;
+
+ default:
+ printf("sm501 system config : not implemented register read."
+ " addr=%x, offset=%x\n", addr, offset);
+ assert(0);
+ }
+
+ return ret;
+}
+
+static void sm501_system_config_write(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
+ SM501_DPRINTF("sm501 system config regs : write addr=%x, ofs=%x, val=%x\n",
+ addr, offset, value);
+
+ switch(offset) {
+ case SM501_SYSTEM_CONTROL:
+ s->system_control = value & 0xE300B8F7;
+ break;
+ case SM501_MISC_CONTROL:
+ s->misc_control = value & 0xFF7FFF20;
+ break;
+ case SM501_GPIO31_0_CONTROL:
+ s->gpio_31_0_control = value;
+ break;
+ case SM501_GPIO63_32_CONTROL:
+ s->gpio_63_32_control = value;
+ break;
+ case SM501_DRAM_CONTROL:
+ s->local_mem_size_index = (value >> 13) & 0x7;
+ /* rODO : check validity of size change */
+ s->dram_control |= value & 0x7FFFFFC3;
+ break;
+ case SM501_IRQ_MASK:
+ s->irq_mask = value;
+ break;
+ case SM501_MISC_TIMING:
+ s->misc_timing = value & 0xF31F1FFF;
+ break;
+ case SM501_POWER_MODE_0_GATE:
+ case SM501_POWER_MODE_1_GATE:
+ case SM501_POWER_MODE_0_CLOCK:
+ case SM501_POWER_MODE_1_CLOCK:
+ /* TODO : simulate gate & clock control */
+ break;
+ case SM501_POWER_MODE_CONTROL:
+ s->power_mode_control = value & 0x00000003;
+ break;
+
+ default:
+ printf("sm501 system config : not implemented register write."
+ " addr=%x, val=%x\n", addr, value);
+ assert(0);
+ }
+}
+
+static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
+ NULL,
+ NULL,
+ &sm501_system_config_read,
+};
+
+static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
+ NULL,
+ NULL,
+ &sm501_system_config_write,
+};
+
+static uint32_t sm501_disp_ctrl_read(void *opaque,
+ target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
+ uint32_t ret = 0;
+ SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x, offset=%x\n",
+ addr, offset);
+
+ switch(offset) {
+
+ case SM501_DC_PANEL_CONTROL:
+ ret = s->dc_panel_control;
+ break;
+ case SM501_DC_PANEL_PANNING_CONTROL:
+ ret = s->dc_panel_panning_control;
+ break;
+ case SM501_DC_PANEL_FB_ADDR:
+ ret = s->dc_panel_fb_addr;
+ break;
+ case SM501_DC_PANEL_FB_OFFSET:
+ ret = s->dc_panel_fb_offset;
+ break;
+ case SM501_DC_PANEL_FB_WIDTH:
+ ret = s->dc_panel_fb_width;
+ break;
+ case SM501_DC_PANEL_FB_HEIGHT:
+ ret = s->dc_panel_fb_height;
+ break;
+ case SM501_DC_PANEL_TL_LOC:
+ ret = s->dc_panel_tl_location;
+ break;
+ case SM501_DC_PANEL_BR_LOC:
+ ret = s->dc_panel_br_location;
+ break;
+
+ case SM501_DC_PANEL_H_TOT:
+ ret = s->dc_panel_h_total;
+ break;
+ case SM501_DC_PANEL_H_SYNC:
+ ret = s->dc_panel_h_sync;
+ break;
+ case SM501_DC_PANEL_V_TOT:
+ ret = s->dc_panel_v_total;
+ break;
+ case SM501_DC_PANEL_V_SYNC:
+ ret = s->dc_panel_v_sync;
+ break;
+
+ case SM501_DC_CRT_CONTROL:
+ ret = s->dc_crt_control;
+ break;
+ case SM501_DC_CRT_FB_ADDR:
+ ret = s->dc_crt_fb_addr;
+ break;
+ case SM501_DC_CRT_FB_OFFSET:
+ ret = s->dc_crt_fb_offset;
+ break;
+ case SM501_DC_CRT_H_TOT:
+ ret = s->dc_crt_h_total;
+ break;
+ case SM501_DC_CRT_H_SYNC:
+ ret = s->dc_crt_h_sync;
+ break;
+ case SM501_DC_CRT_V_TOT:
+ ret = s->dc_crt_v_total;
+ break;
+ case SM501_DC_CRT_V_SYNC:
+ ret = s->dc_crt_v_sync;
+ break;
+
+ case SM501_DC_CRT_HWC_ADDR:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC_CRT_HWC_LOC:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_1_2:
+ ret = s->dc_crt_hwc_addr;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_3:
+ ret = s->dc_crt_hwc_addr;
+ break;
+
+ default:
+ printf("sm501 disp ctrl : not implemented register read."
+ " addr=%x, offset=%x\n", addr, offset);
+ assert(0);
+ }
+
+ return ret;
+}
+
+static void sm501_disp_ctrl_write(void *opaque,
+ target_phys_addr_t addr,
+ uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
+ SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, ofs=%x, val=%x\n",
+ addr, offset, value);
+
+ switch(offset) {
+ case SM501_DC_PANEL_CONTROL:
+ s->dc_panel_control = value & 0x0FFF73FF;
+ break;
+ case SM501_DC_PANEL_PANNING_CONTROL:
+ s->dc_panel_panning_control = value & 0xFF3FFF3F;
+ break;
+ case SM501_DC_PANEL_FB_ADDR:
+ s->dc_panel_fb_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_PANEL_FB_OFFSET:
+ s->dc_panel_fb_offset = value & 0x3FF03FF0;
+ break;
+ case SM501_DC_PANEL_FB_WIDTH:
+ s->dc_panel_fb_width = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_FB_HEIGHT:
+ s->dc_panel_fb_height = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_TL_LOC:
+ s->dc_panel_tl_location = value & 0x07FF07FF;
+ break;
+ case SM501_DC_PANEL_BR_LOC:
+ s->dc_panel_br_location = value & 0x07FF07FF;
+ break;
+
+ case SM501_DC_PANEL_H_TOT:
+ s->dc_panel_h_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_H_SYNC:
+ s->dc_panel_h_sync = value & 0x00FF0FFF;
+ break;
+ case SM501_DC_PANEL_V_TOT:
+ s->dc_panel_v_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_V_SYNC:
+ s->dc_panel_v_sync = value & 0x003F0FFF;
+ break;
+
+ case SM501_DC_PANEL_HWC_ADDR:
+ s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_PANEL_HWC_LOC:
+ s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_PANEL_HWC_COLOR_1_2:
+ s->dc_panel_hwc_addr = value;
+ break;
+ case SM501_DC_PANEL_HWC_COLOR_3:
+ s->dc_panel_hwc_addr = value & 0x0000FFFF;
+ break;
+
+ case SM501_DC_CRT_CONTROL:
+ s->dc_crt_control = value & 0x0003FFFF;
+ break;
+ case SM501_DC_CRT_FB_ADDR:
+ s->dc_crt_fb_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_CRT_FB_OFFSET:
+ s->dc_crt_fb_offset = value & 0x3FF03FF0;
+ break;
+ case SM501_DC_CRT_H_TOT:
+ s->dc_crt_h_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_CRT_H_SYNC:
+ s->dc_crt_h_sync = value & 0x00FF0FFF;
+ break;
+ case SM501_DC_CRT_V_TOT:
+ s->dc_crt_v_total = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_CRT_V_SYNC:
+ s->dc_crt_v_sync = value & 0x003F0FFF;
+ break;
+
+ case SM501_DC_CRT_HWC_ADDR:
+ s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
+ break;
+ case SM501_DC_CRT_HWC_LOC:
+ s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_1_2:
+ s->dc_crt_hwc_addr = value;
+ break;
+ case SM501_DC_CRT_HWC_COLOR_3:
+ s->dc_crt_hwc_addr = value & 0x0000FFFF;
+ break;
+
+ default:
+ printf("sm501 disp ctrl : not implemented register write."
+ " addr=%x, val=%x\n", addr, value);
+ assert(0);
+ }
+}
+
+static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
+ NULL,
+ NULL,
+ &sm501_disp_ctrl_read,
+};
+
+static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
+ NULL,
+ NULL,
+ &sm501_disp_ctrl_write,
+};
+
+static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
+ + SM501_DC + SM501_DC_PANEL_PALETTE);
+ SM501_DPRINTF("sm501 palette read addr=%x, offset=%x\n", addr, offset);
+
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+
+ assert(0 <= offset && offset < 0x400 * 3);
+ return *(uint32_t*)&s->dc_palette[offset];
+}
+
+static void sm501_palette_write(void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SM501State * s = (SM501State *)opaque;
+ uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
+ + SM501_DC + SM501_DC_PANEL_PALETTE);
+ SM501_DPRINTF("sm501 palette write addr=%x, ofs=%x, val=%x\n",
+ addr, offset, value);
+
+ /* TODO : consider BYTE/WORD access */
+ /* TODO : consider endian */
+
+ assert(0 <= offset && offset < 0x400 * 3);
+ *(uint32_t*)&s->dc_palette[offset] = value;
+}
+
+static CPUReadMemoryFunc *sm501_palette_readfn[] = {
+ &sm501_palette_read,
+ &sm501_palette_read,
+ &sm501_palette_read,
+};
+
+static CPUWriteMemoryFunc *sm501_palette_writefn[] = {
+ &sm501_palette_write,
+ &sm501_palette_write,
+ &sm501_palette_write,
+};
+
+
+/* draw line functions for all console modes */
+
+#include "pixel_ops.h"
+
+typedef void draw_line_func(uint8_t *d, const uint8_t *s,
+ int width, const uint32_t *pal);
+
+#define DEPTH 8
+#include "sm501_template.h"
+
+#define DEPTH 15
+#include "sm501_template.h"
+
+#define BGR_FORMAT
+#define DEPTH 15
+#include "sm501_template.h"
+
+#define DEPTH 16
+#include "sm501_template.h"
+
+#define BGR_FORMAT
+#define DEPTH 16
+#include "sm501_template.h"
+
+#define DEPTH 32
+#include "sm501_template.h"
+
+#define BGR_FORMAT
+#define DEPTH 32
+#include "sm501_template.h"
+
+static draw_line_func * draw_line8_funcs[] = {
+ draw_line8_8,
+ draw_line8_15,
+ draw_line8_16,
+ draw_line8_32,
+ draw_line8_32bgr,
+ draw_line8_15bgr,
+ draw_line8_16bgr,
+};
+
+static draw_line_func * draw_line16_funcs[] = {
+ draw_line16_8,
+ draw_line16_15,
+ draw_line16_16,
+ draw_line16_32,
+ draw_line16_32bgr,
+ draw_line16_15bgr,
+ draw_line16_16bgr,
+};
+
+static draw_line_func * draw_line32_funcs[] = {
+ draw_line32_8,
+ draw_line32_15,
+ draw_line32_16,
+ draw_line32_32,
+ draw_line32_32bgr,
+ draw_line32_15bgr,
+ draw_line32_16bgr,
+};
+
+static inline int get_depth_index(DisplayState *s)
+{
+ switch(s->depth) {
+ default:
+ case 8:
+ return 0;
+ case 15:
+ if (s->bgr)
+ return 5;
+ else
+ return 1;
+ case 16:
+ if (s->bgr)
+ return 6;
+ else
+ return 2;
+ case 32:
+ if (s->bgr)
+ return 4;
+ else
+ return 3;
+ }
+}
+
+static void sm501_draw_crt(SM501State * s)
+{
+ int y;
+ int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
+ int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
+
+ uint8_t * src = s->local_mem;
+ int src_bpp = 0;
+ int dst_bpp = s->ds->depth / 8 + (s->ds->depth % 8 ? 1 : 0);
+ uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
+ - SM501_DC_PANEL_PALETTE];
+ int ds_depth_index = get_depth_index(s->ds);
+ draw_line_func * draw_line = NULL;
+ int full_update = 0;
+ int y_start = -1;
+ int page_min = 0x7fffffff;
+ int page_max = -1;
+
+ /* choose draw_line function */
+ switch (s->dc_crt_control & 3) {
+ case SM501_DC_CRT_CONTROL_8BPP:
+ src_bpp = 1;
+ draw_line = draw_line8_funcs[ds_depth_index];
+ break;
+ case SM501_DC_CRT_CONTROL_16BPP:
+ src_bpp = 2;
+ draw_line = draw_line16_funcs[ds_depth_index];
+ break;
+ case SM501_DC_CRT_CONTROL_32BPP:
+ src_bpp = 4;
+ draw_line = draw_line32_funcs[ds_depth_index];
+ break;
+ default:
+ printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
+ s->dc_crt_control);
+ assert(0);
+ break;
+ }
+
+ /* adjust console size */
+ if (s->last_width != width || s->last_height != height) {
+ qemu_console_resize(s->console, width, height);
+ s->last_width = width;
+ s->last_height = height;
+ full_update = 1;
+ }
+
+ /* draw each line according to conditions */
+ for (y = 0; y < height; y++) {
+ int update = full_update;
+ uint8_t * line_end = &src[width * src_bpp - 1];
+ int page0 = (src - phys_ram_base) & TARGET_PAGE_MASK;
+ int page1 = (line_end - phys_ram_base) & TARGET_PAGE_MASK;
+ int page;
+
+ /* check dirty flags for each line */
+ for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
+ if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
+ update = 1;
+
+ /* draw line and change status */
+ if (update) {
+ draw_line(&s->ds->data[y * width * dst_bpp], src, width, palette);
+ if (y_start < 0)
+ y_start = y;
+ if (page0 < page_min)
+ page_min = page0;
+ if (page1 > page_max)
+ page_max = page1;
+ } else {
+ if (y_start >= 0) {
+ /* flush to display */
+ dpy_update(s->ds, 0, y_start, width, y - y_start);
+ y_start = -1;
+ }
+ }
+
+ src += width * src_bpp;
+ }
+
+ /* complete flush to display */
+ if (y_start >= 0)
+ dpy_update(s->ds, 0, y_start, width, y - y_start);
+
+ /* clear dirty flags */
+ if (page_max != -1)
+ cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
+ VGA_DIRTY_FLAG);
+}
+
+static void sm501_update_display(void *opaque)
+{
+ SM501State * s = (SM501State *)opaque;
+
+ if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
+ sm501_draw_crt(s);
+}
+
+void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
+ uint32_t local_mem_bytes, CharDriverState *chr)
+{
+ SM501State * s;
+ int sm501_system_config_index;
+ int sm501_disp_ctrl_index;
+ int sm501_palette_index;
+
+ /* allocate management data region */
+ s = (SM501State *)qemu_mallocz(sizeof(SM501State));
+ s->base = base;
+ s->local_mem_size_index
+ = get_local_mem_size_index(local_mem_bytes);
+ SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
+ s->local_mem_size_index);
+ s->system_control = 0x00100000;
+ s->misc_control = 0x00001000; /* assumes SH, active=low */
+ s->dc_panel_control = 0x00010000;
+ s->dc_crt_control = 0x00010000;
+ s->ds = ds;
+
+ /* allocate local memory */
+ s->local_mem = (uint8 *)phys_ram_base + local_mem_base;
+ cpu_register_physical_memory(base, local_mem_bytes, local_mem_base);
+
+ /* map mmio */
+ sm501_system_config_index
+ = cpu_register_io_memory(0, sm501_system_config_readfn,
+ sm501_system_config_writefn, s);
+ cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
+ 0x6c, sm501_system_config_index);
+ sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn,
+ sm501_disp_ctrl_writefn, s);
+ cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
+ 0x400, sm501_disp_ctrl_index);
+
+ sm501_palette_index = cpu_register_io_memory(0, sm501_palette_readfn,
+ sm501_palette_writefn, s);
+ cpu_register_physical_memory(base + MMIO_BASE_OFFSET
+ + SM501_DC + SM501_DC_PANEL_PALETTE,
+ 0x400 * 3, sm501_palette_index);
+
+ /* bridge to serial emulation module */
+ if (chr)
+ serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
+ 0, /* TODO : chain irq to IRL */
+ 115200, chr, 1);
+
+ /* create qemu graphic console */
+ s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
+ NULL, NULL, s);
+}
Index: trunk/hw/sm501_template.h
===================================================================
--- trunk/hw/sm501_template.h (revision 0)
+++ trunk/hw/sm501_template.h (revision 0)
@@ -0,0 +1,104 @@
+/*
+ * Pixel drawing function templates for QEMU SM501 Device
+ *
+ * Copyright (c) 2008 Shin-ichiro KAWASAKI
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if DEPTH == 8
+#define BPP 1
+#define PIXEL_TYPE uint8_t
+#elif DEPTH == 15 || DEPTH == 16
+#define BPP 2
+#define PIXEL_TYPE uint16_t
+#elif DEPTH == 32
+#define BPP 4
+#define PIXEL_TYPE uint32_t
+#else
+#error unsupport depth
+#endif
+
+#ifdef BGR_FORMAT
+#define PIXEL_NAME glue(DEPTH, bgr)
+#else
+#define PIXEL_NAME DEPTH
+#endif /* BGR_FORMAT */
+
+
+static void glue(draw_line8_, PIXEL_NAME)(
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+{
+ uint8_t v, r, g, b;
+ do {
+ v = ldub_raw(s);
+ r = (pal[v] >> 16) & 0xff;
+ g = (pal[v] >> 8) & 0xff;
+ b = (pal[v] >> 0) & 0xff;
+ ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s ++;
+ d += BPP;
+ } while (-- width != 0);
+}
+
+static void glue(draw_line16_, PIXEL_NAME)(
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+{
+ uint16_t rgb565;
+ uint8_t r, g, b;
+
+ do {
+ rgb565 = lduw_raw(s);
+ r = ((rgb565 >> 11) & 0x1f) << 3;
+ g = ((rgb565 >> 5) & 0x3f) << 2;
+ b = ((rgb565 >> 0) & 0x1f) << 3;
+ ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s += 2;
+ d += BPP;
+ } while (-- width != 0);
+}
+
+static void glue(draw_line32_, PIXEL_NAME)(
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+{
+ uint8_t r, g, b;
+
+ do {
+ ldub_raw(s);
+#if defined(TARGET_WORDS_BIGENDIAN)
+ r = s[1];
+ g = s[2];
+ b = s[3];
+#else
+ b = s[0];
+ g = s[1];
+ r = s[2];
+#endif
+ ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s += 4;
+ d += BPP;
+ } while (-- width != 0);
+}
+
+#undef DEPTH
+#undef BPP
+#undef PIXEL_TYPE
+#undef PIXEL_NAME
+#undef BGR_FORMAT
+
Index: trunk/hw/devices.h
===================================================================
--- trunk/hw/devices.h (revision 5594)
+++ trunk/hw/devices.h (working copy)
@@ -71,4 +71,7 @@
qemu_irq handler);
qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
+/* sm501.c */
+void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
+ uint32_t local_mem_bytes, CharDriverState *chr);
#endif
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] [RESEND] SM501 emulation for R2D-SH4
2008-11-05 17:09 ` [Qemu-devel] [PATCH] [RESEND] " Shin-ichiro KAWASAKI
@ 2008-11-05 18:25 ` Blue Swirl
2008-11-05 20:13 ` andrzej zaborowski
0 siblings, 1 reply; 14+ messages in thread
From: Blue Swirl @ 2008-11-05 18:25 UTC (permalink / raw)
To: qemu-devel, andrzej zaborowski
On 11/5/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> Blue Swirl wrote:
>
> > On 11/4/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> >
> > > Thank you for reviewing!
> > >
> > > I add the new version of patch to this mail, which reflects
> > > you and andrzej's comments. Some more comments on it will be
> > > appreciated. Especially advice on VRAM implementation with
> > > normal RAM will be useful for me.
> > >
> > > > The display buffer should be allocated using machine definition
> > > >
> > > .ram_require.
> > > I tried normal RAM implementation : "#define USE_NORMAL_RAM" in the
> patch
> > > will
> > > turn the new implementation on. But it causes system hang during
> SH-Linux
> > > boot up.
> > > The initial VRAM clearance seems to cause the hang.
> > > The reason might be my wrong implementation, or any MMU problem of SH4.
> > >
> > > I did,
> > > - added VRAM size to .ram_require
> > > - invoked qemu_ram_alloc() with the VRAM size parameter,
> > > - and invoked cpu_register_physical_memory(), passing
> the
> > > return value of
> > > qemu_ram_alloc() as third parameter.
> > >
> > > Is this sequence correct?
> > >
> >
> > Yes, but the system RAM is not allocated using qemu_ram_alloc. Now
> > qemu_ram_alloc gives the same area (0 to VRAM_SIZE) the second time.
> >
> > So the following:
> > /* Allocate memory space */
> > cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE,
> 0);
> > should be changed to:
> > ram_addr = qemu_ram_alloc(SDRAM_SIZE);
> > cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE,
> ram_addr);
> >
> > Maybe that helps?
> >
>
> Yes, it helps. Thank you!
>
> Here's the new patch which uses normal RAM as the VRAM, and
> checks VGA_DIRTY_FLAG for partial update.
>
> I think it is ready for merge to the trunk.
> Could anyone help it?
Looks good to me. What about you, Andrzej?
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] [RESEND] SM501 emulation for R2D-SH4
2008-11-05 18:25 ` Blue Swirl
@ 2008-11-05 20:13 ` andrzej zaborowski
2008-11-05 20:26 ` Blue Swirl
0 siblings, 1 reply; 14+ messages in thread
From: andrzej zaborowski @ 2008-11-05 20:13 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
2008/11/5 Blue Swirl <blauwirbel@gmail.com>:
> On 11/5/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
>> Blue Swirl wrote:
>>
>> > On 11/4/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
>> >
>> > > Thank you for reviewing!
>> > >
>> > > I add the new version of patch to this mail, which reflects
>> > > you and andrzej's comments. Some more comments on it will be
>> > > appreciated. Especially advice on VRAM implementation with
>> > > normal RAM will be useful for me.
>> > >
>> > > > The display buffer should be allocated using machine definition
>> > > >
>> > > .ram_require.
>> > > I tried normal RAM implementation : "#define USE_NORMAL_RAM" in the
>> patch
>> > > will
>> > > turn the new implementation on. But it causes system hang during
>> SH-Linux
>> > > boot up.
>> > > The initial VRAM clearance seems to cause the hang.
>> > > The reason might be my wrong implementation, or any MMU problem of SH4.
>> > >
>> > > I did,
>> > > - added VRAM size to .ram_require
>> > > - invoked qemu_ram_alloc() with the VRAM size parameter,
>> > > - and invoked cpu_register_physical_memory(), passing
>> the
>> > > return value of
>> > > qemu_ram_alloc() as third parameter.
>> > >
>> > > Is this sequence correct?
>> > >
>> >
>> > Yes, but the system RAM is not allocated using qemu_ram_alloc. Now
>> > qemu_ram_alloc gives the same area (0 to VRAM_SIZE) the second time.
>> >
>> > So the following:
>> > /* Allocate memory space */
>> > cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE,
>> 0);
>> > should be changed to:
>> > ram_addr = qemu_ram_alloc(SDRAM_SIZE);
>> > cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE,
>> ram_addr);
>> >
>> > Maybe that helps?
>> >
>>
>> Yes, it helps. Thank you!
>>
>> Here's the new patch which uses normal RAM as the VRAM, and
>> checks VGA_DIRTY_FLAG for partial update.
>>
>> I think it is ready for merge to the trunk.
>> Could anyone help it?
>
> Looks good to me. What about you, Andrzej?
While I don't know the hardware, it looks correct to me, feel free to merge.
One nit is that qemu_ram_alloc() makes it possible for ram to be
allocked inside devices, so for example the local_mem_base and
local_mem_bytes parameters can be removed.
Cheers
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH] [RESEND] SM501 emulation for R2D-SH4
2008-11-05 20:13 ` andrzej zaborowski
@ 2008-11-05 20:26 ` Blue Swirl
0 siblings, 0 replies; 14+ messages in thread
From: Blue Swirl @ 2008-11-05 20:26 UTC (permalink / raw)
To: andrzej zaborowski; +Cc: qemu-devel
On 11/5/08, andrzej zaborowski <balrogg@gmail.com> wrote:
> 2008/11/5 Blue Swirl <blauwirbel@gmail.com>:
>
> > On 11/5/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> >> Blue Swirl wrote:
> >>
> >> > On 11/4/08, Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp> wrote:
> >> >
> >> > > Thank you for reviewing!
> >> > >
> >> > > I add the new version of patch to this mail, which reflects
> >> > > you and andrzej's comments. Some more comments on it will be
> >> > > appreciated. Especially advice on VRAM implementation with
> >> > > normal RAM will be useful for me.
> >> > >
> >> > > > The display buffer should be allocated using machine definition
> >> > > >
> >> > > .ram_require.
> >> > > I tried normal RAM implementation : "#define USE_NORMAL_RAM" in the
> >> patch
> >> > > will
> >> > > turn the new implementation on. But it causes system hang during
> >> SH-Linux
> >> > > boot up.
> >> > > The initial VRAM clearance seems to cause the hang.
> >> > > The reason might be my wrong implementation, or any MMU problem of SH4.
> >> > >
> >> > > I did,
> >> > > - added VRAM size to .ram_require
> >> > > - invoked qemu_ram_alloc() with the VRAM size parameter,
> >> > > - and invoked cpu_register_physical_memory(), passing
> >> the
> >> > > return value of
> >> > > qemu_ram_alloc() as third parameter.
> >> > >
> >> > > Is this sequence correct?
> >> > >
> >> >
> >> > Yes, but the system RAM is not allocated using qemu_ram_alloc. Now
> >> > qemu_ram_alloc gives the same area (0 to VRAM_SIZE) the second time.
> >> >
> >> > So the following:
> >> > /* Allocate memory space */
> >> > cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE,
> >> 0);
> >> > should be changed to:
> >> > ram_addr = qemu_ram_alloc(SDRAM_SIZE);
> >> > cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE,
> >> ram_addr);
> >> >
> >> > Maybe that helps?
> >> >
> >>
> >> Yes, it helps. Thank you!
> >>
> >> Here's the new patch which uses normal RAM as the VRAM, and
> >> checks VGA_DIRTY_FLAG for partial update.
> >>
> >> I think it is ready for merge to the trunk.
> >> Could anyone help it?
> >
> > Looks good to me. What about you, Andrzej?
>
>
> While I don't know the hardware, it looks correct to me, feel free to merge.
Committed as r5632. Thanks!
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2008-11-05 20:26 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-11-02 2:12 [Qemu-devel] [PATCH] SM501 emulation for R2D-SH4 Shin-ichiro KAWASAKI
2008-11-02 3:27 ` andrzej zaborowski
2008-11-04 14:31 ` Shin-ichiro KAWASAKI
2008-11-02 6:52 ` Blue Swirl
2008-11-04 15:10 ` Shin-ichiro KAWASAKI
2008-11-04 19:11 ` Blue Swirl
2008-11-05 17:09 ` [Qemu-devel] [PATCH] [RESEND] " Shin-ichiro KAWASAKI
2008-11-05 18:25 ` Blue Swirl
2008-11-05 20:13 ` andrzej zaborowski
2008-11-05 20:26 ` Blue Swirl
2008-11-04 15:27 ` [Qemu-devel] When should I use qemu_ram_alloc(), and how? takasi-y
2008-11-04 19:14 ` [Qemu-devel] " Blue Swirl
2008-11-04 19:32 ` Anthony Liguori
2008-11-05 13:29 ` takasi-y
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