From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ky8XI-0005MC-1i for qemu-devel@nongnu.org; Thu, 06 Nov 2008 12:20:48 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ky8XG-0005LM-AW for qemu-devel@nongnu.org; Thu, 06 Nov 2008 12:20:47 -0500 Received: from [199.232.76.173] (port=48262 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ky8XG-0005LF-1h for qemu-devel@nongnu.org; Thu, 06 Nov 2008 12:20:46 -0500 Received: from lizzard.sbs.de ([194.138.37.39]:17709) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Ky8XF-0008Ut-VK for qemu-devel@nongnu.org; Thu, 06 Nov 2008 12:20:46 -0500 Message-ID: <4913275A.1060600@siemens.com> Date: Thu, 06 Nov 2008 18:20:26 +0100 From: Jan Kiszka MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] Fix interrupt exclusion via SSTEP_NOIRQ Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Jan Kiszka Commit #5620 revealed an issue of the SSTEP_NOIRQ masking that was applied on all interrupt sources (including internal ones) when single stepping through the guest. Due to that commit, we now ended up in an infinite loop when CPU_INTERRUPT_EXIT was pending on SSTEP resume. That was due to #5620 eating all TBs while CPU_INTERRUPT_EXIT is pending, but SSTEP_NOIRQ preventing CPU_INTERRUPT_EXIT to be processed. What SSTEP_NOIRQ should actually do is to block the delivery of all external, guest visible interrupts. With the fix below applied, single stepping now works again. Signed-off-by: Jan Kiszka --- cpu-exec.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) Index: b/cpu-exec.c =================================================================== --- a/cpu-exec.c +++ b/cpu-exec.c @@ -384,8 +384,14 @@ int cpu_exec(CPUState *env1) next_tb = 0; /* force lookup of first TB */ for(;;) { interrupt_request = env->interrupt_request; - if (unlikely(interrupt_request) && - likely(!(env->singlestep_enabled & SSTEP_NOIRQ))) { + if (unlikely(interrupt_request)) { + if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { + /* Mask out external interrupts for this step. */ + interrupt_request &= ~(CPU_INTERRUPT_HARD | + CPU_INTERRUPT_FIQ | + CPU_INTERRUPT_SMI | + CPU_INTERRUPT_NMI); + } if (interrupt_request & CPU_INTERRUPT_DEBUG) { env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; env->exception_index = EXCP_DEBUG; -- Siemens AG, Corporate Technology, CT SE 2 ES-OS Corporate Competence Center Embedded Linux