From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KypEZ-0001vJ-V8 for qemu-devel@nongnu.org; Sat, 08 Nov 2008 09:56:20 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KypEX-0001tp-95 for qemu-devel@nongnu.org; Sat, 08 Nov 2008 09:56:18 -0500 Received: from [199.232.76.173] (port=35798 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KypEW-0001tl-O0 for qemu-devel@nongnu.org; Sat, 08 Nov 2008 09:56:16 -0500 Received: from smtp6-g19.free.fr ([212.27.42.36]:39795) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KypEW-0005UB-D9 for qemu-devel@nongnu.org; Sat, 08 Nov 2008 09:56:16 -0500 Received: from smtp6-g19.free.fr (localhost.localdomain [127.0.0.1]) by smtp6-g19.free.fr (Postfix) with ESMTP id B98B619713 for ; Sat, 8 Nov 2008 15:56:13 +0100 (CET) Received: from [192.168.0.32] (rob92-10-88-171-126-33.fbx.proxad.net [88.171.126.33]) by smtp6-g19.free.fr (Postfix) with ESMTP id 21FBD1973A for ; Sat, 8 Nov 2008 15:56:11 +0100 (CET) Message-ID: <4915A887.9090003@reactos.org> Date: Sat, 08 Nov 2008 15:56:07 +0100 From: =?ISO-8859-1?Q?Herv=E9_Poussineau?= MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------070603070001010708040502" Subject: [Qemu-devel] [PATCH] MIPS: DMA support for RC4030 chipset [v2] Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------070603070001010708040502 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Hi, Attached patch implements DMA support to RC4030 chipset and simplifies=20 jazz IO part (at 0xf0000000), where registers contain 16 bit values. The patch also wires DMA transfers for the SCSI adapter in the Jazz=20 emulation (Mips Magnum 4000 and Acer Pica 61). Blue Swirl's comments have been taken into account in this version: Changes since v1: - Support reuse of esp callback functions up to DMA engine - Don't keep in memory the DMA table, but read it when needed Herv=E9 --------------070603070001010708040502 Content-Type: plain/text; name="rc4030_dma_v2.diff" Content-Disposition: inline; filename="rc4030_dma_v2.diff" Content-Transfer-Encoding: quoted-printable Index: hw/mips.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- hw/mips.h (revision 5649) +++ hw/mips.h (working copy) @@ -27,6 +27,9 @@ extern void cpu_mips_clock_init(CPUState *); =20 /* rc4030.c */ -qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus); +typedef struct rc4030DMAState *rc4030_dma; +typedef void (*rc4030_dma_function)(void *dma, uint8_t *buf, int len); +qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, rc4030_dma **dm= as, + rc4030_dma_function *dma_read, rc4030_dma_function= *dma_write); =20 #endif Index: hw/mips_jazz.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- hw/mips_jazz.c (revision 5649) +++ hw/mips_jazz.c (working copy) @@ -102,16 +102,6 @@ } #endif =20 -void espdma_memory_read(void *opaque, uint8_t *buf, int len) -{ - printf("espdma_memory_read(buf %p, len %d) not implemented\n", buf, = len); -} - -void espdma_memory_write(void *opaque, uint8_t *buf, int len) -{ - printf("espdma_memory_write(buf %p, len %d) not implemented\n", buf,= len); -} - #define MAGNUM_BIOS_SIZE_MAX 0x7e000 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE := MAGNUM_BIOS_SIZE_MAX) =20 @@ -125,6 +115,8 @@ int bios_size, n; CPUState *env; qemu_irq *rc4030, *i8259; + rc4030_dma *dmas; + rc4030_dma_function dma_read, dma_write; void *scsi_hba; int hd; int s_rtc; @@ -171,7 +163,8 @@ cpu_mips_clock_init(env); =20 /* Chipset */ - rc4030 =3D rc4030_init(env->irq[6], env->irq[3]); + rc4030 =3D rc4030_init(env->irq[6], env->irq[3], + &dmas, &dma_read, &dma_write); =20 /* ISA devices */ i8259 =3D i8259_init(env->irq[4]); @@ -200,7 +193,7 @@ =20 /* SCSI adapter */ scsi_hba =3D esp_init(0x80002000, 0, - espdma_memory_read, espdma_memory_write, NULL, + dma_read, dma_write, dmas[0], rc4030[5], &esp_reset); for (n =3D 0; n < ESP_MAX_DEVS; n++) { hd =3D drive_get_index(IF_SCSI, 0, n); @@ -278,6 +271,7 @@ .init =3D mips_magnum_init, .ram_require =3D MAGNUM_BIOS_SIZE + VGA_RAM_SIZE, .nodisk_ok =3D 1, + .use_scsi =3D 1, }; =20 QEMUMachine mips_pica61_machine =3D { @@ -286,4 +280,5 @@ .init =3D mips_pica61_init, .ram_require =3D MAGNUM_BIOS_SIZE + VGA_RAM_SIZE, .nodisk_ok =3D 1, + .use_scsi =3D 1, }; Index: hw/rc4030.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- hw/rc4030.c (revision 5649) +++ hw/rc4030.c (working copy) @@ -1,7 +1,7 @@ /* * QEMU JAZZ RC4030 chipset * - * Copyright (c) 2007-2008 Herv=C3=A9 Poussineau + * Copyright (c) 2007-2008 Herve Poussineau * * Permission is hereby granted, free of charge, to any person obtaining= a copy * of this software and associated documentation files (the "Software"),= to deal @@ -23,15 +23,43 @@ */ =20 #include "hw.h" +#include "mips.h" #include "qemu-timer.h" =20 +/********************************************************/ +/* debug rc4030 */ + //#define DEBUG_RC4030 +//#define DEBUG_RC4030_DMA =20 #ifdef DEBUG_RC4030 +#define DPRINTF(fmt, args...) \ +do { printf("rc4030: " fmt , ##args); } while (0) static const char* irq_names[] =3D { "parallel", "floppy", "sound", "vid= eo", "network", "scsi", "keyboard", "mouse", "serial0", "serial1"= }; +#else +#define DPRINTF(fmt, args...) #endif =20 +#define RC4030_ERROR(fmt, args...) \ +do { printf("rc4030 ERROR: %s: " fmt, __func__ , ##args); } while (0) + +/********************************************************/ +/* rc4030 emulation */ + +typedef struct dma_pagetable_entry { + int32_t frame; + int32_t owner; +} __attribute__((packed)) dma_pagetable_entry; + +#define DMA_PAGESIZE 4096 +#define DMA_REG_ENABLE 1 +#define DMA_REG_COUNT 2 +#define DMA_REG_ADDRESS 3 + +#define DMA_FLAG_ENABLE 0x1 +#define DMA_FLAG_MEM_TO_DEV 0x2 + typedef struct rc4030State { uint32_t config; /* 0x0000: RC4030 config register */ @@ -39,7 +67,7 @@ =20 /* DMA */ uint32_t dma_regs[8][4]; - uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */ + target_phys_addr_t dma_tl_base; /* 0x0018: DMA transl. table base */ uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */ =20 /* cache */ @@ -50,7 +78,6 @@ uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */ uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */ =20 - uint32_t offset208; uint32_t offset210; uint32_t nvram_protect; /* 0x0220: NV ram protect register */ uint32_t offset238; @@ -62,7 +89,6 @@ QEMUTimer *periodic_timer; uint32_t itr; /* Interval timer reload */ =20 - uint32_t dummy32; qemu_irq timer_irq; qemu_irq jazz_bus_irq; } rc4030State; @@ -164,7 +190,7 @@ case 0x01d0: case 0x01d8: case 0x01e0: - case 0x1e8: + case 0x01e8: case 0x01f0: case 0x01f8: { @@ -175,7 +201,7 @@ break; /* Offset 0x0208 */ case 0x0208: - val =3D s->offset208; + val =3D 0; break; /* Offset 0x0210 */ case 0x0210: @@ -187,7 +213,7 @@ break; /* Interval timer count */ case 0x0230: - val =3D s->dummy32; + val =3D 0; qemu_irq_lower(s->timer_irq); break; /* Offset 0x0238 */ @@ -195,17 +221,13 @@ val =3D s->offset238; break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr); -#endif + RC4030_ERROR("invalid read [" TARGET_FMT_lx "]\n", addr); val =3D 0; break; } =20 -#ifdef DEBUG_RC4030 if ((addr & ~3) !=3D 0x230) - printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr); -#endif + DPRINTF("read 0x%02x at " TARGET_FMT_lx "\n", val, addr); =20 return val; } @@ -230,9 +252,7 @@ rc4030State *s =3D opaque; addr &=3D 0x3fff; =20 -#ifdef DEBUG_RC4030 - printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr); -#endif + DPRINTF("write 0x%02x at " TARGET_FMT_lx "\n", val, addr); =20 switch (addr & ~0x3) { /* Global config register */ @@ -241,12 +261,20 @@ break; /* DMA transl. table base */ case 0x0018: - s->dma_tl_base =3D val; + s->dma_tl_base =3D (int32_t)val; break; /* DMA transl. table limit */ case 0x0020: s->dma_tl_limit =3D val; break; + /* DMA transl. table invalidated */ + case 0x0028: + /* Nothing to do; we don't keep the table in memory */ + break; + /* Cache Maintenance */ + case 0x0030: + RC4030_ERROR("Cache maintenance not handled yet (val 0x%02x)\n",= val); + break; /* I/O Cache Physical Tag */ case 0x0048: s->cache_ptag =3D val; @@ -321,7 +349,7 @@ case 0x01d0: case 0x01d8: case 0x01e0: - case 0x1e8: + case 0x01e8: case 0x01f0: case 0x01f8: { @@ -341,9 +369,7 @@ set_next_tick(s); break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n= ", val, addr); -#endif + RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_lx "]\n",= val, addr); break; } } @@ -401,7 +427,7 @@ #ifdef DEBUG_RC4030 if (s->isr_jazz !=3D 0) { uint32_t irq =3D 0; - printf("jazz pending:"); + DPRINTF("pending irqs:"); for (irq =3D 0; irq < sizeof(irq_names)/sizeof(irq_names[0]); ir= q++) { if (s->isr_jazz & (1 << irq)) { printf(" %s", irq_names[irq]); @@ -441,7 +467,7 @@ qemu_irq_raise(s->timer_irq); } =20 -static uint32_t int_readb(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) { rc4030State *s =3D opaque; uint32_t val; @@ -449,14 +475,14 @@ addr &=3D 0xfff; =20 switch (addr) { + /* Local bus int source */ case 0x00: { - /* Local bus int source */ uint32_t pending =3D s->isr_jazz & s->imr_jazz; val =3D 0; irq =3D 0; while (pending) { if (pending & 1) { - //printf("returning irq %s\n", irq_names[irq]); + DPRINTF("returning irq %s\n", irq_names[irq]); val =3D (irq + 1) << 2; break; } @@ -465,100 +491,93 @@ } break; } + /* Local bus int enable mask */ + case 0x02: + val =3D s->imr_jazz; + break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) invalid read [" TARGE= T_FMT_lx "]\n", addr); -#endif - val =3D 0; + RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_lx= "]\n", addr); + val =3D 0; } =20 -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_l= x "\n", val, addr); -#endif + DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_lx "\n", v= al, addr); =20 return val; } =20 -static uint32_t int_readw(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr) { uint32_t v; - v =3D int_readb(opaque, addr); - v |=3D int_readb(opaque, addr + 1) << 8; - return v; + v =3D jazzio_readw(opaque, addr & ~0x1); + return (v >> (8 * (addr & 0x1))) & 0xff; } =20 -static uint32_t int_readl(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) { uint32_t v; - v =3D int_readb(opaque, addr); - v |=3D int_readb(opaque, addr + 1) << 8; - v |=3D int_readb(opaque, addr + 2) << 16; - v |=3D int_readb(opaque, addr + 3) << 24; + v =3D jazzio_readw(opaque, addr); + v |=3D jazzio_readw(opaque, addr + 2) << 16; return v; } =20 -static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t v= al) +static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_= t val) { rc4030State *s =3D opaque; addr &=3D 0xfff; =20 -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_= lx "\n", val, addr); -#endif + DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_lx "\n", = val, addr); =20 switch (addr) { /* Local bus int enable mask */ case 0x02: - s->imr_jazz =3D (s->imr_jazz & 0xff00) | (val << 0); update_jazz= _irq(s); + s->imr_jazz =3D val; + update_jazz_irq(s); break; - case 0x03: - s->imr_jazz =3D (s->imr_jazz & 0x00ff) | (val << 8); update_jazz= _irq(s); - break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) invalid write of 0x%02x a= t [" TARGET_FMT_lx "]\n", val, addr); -#endif + RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at ["= TARGET_FMT_lx "]\n", val, addr); break; } } =20 -static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t v= al) +static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_= t val) { - int_writeb(opaque, addr, val & 0xff); - int_writeb(opaque, addr + 1, (val >> 8) & 0xff); + uint32_t old_val =3D jazzio_readw(opaque, addr & ~0x1); + + switch (addr & 1) { + case 0: + val =3D val | (old_val & 0xff00); + break; + case 1: + val =3D (val << 8) | (old_val & 0x00ff); + break; + } + jazzio_writew(opaque, addr & ~0x1, val); } =20 -static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t v= al) +static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_= t val) { - int_writeb(opaque, addr, val & 0xff); - int_writeb(opaque, addr + 1, (val >> 8) & 0xff); - int_writeb(opaque, addr + 2, (val >> 16) & 0xff); - int_writeb(opaque, addr + 3, (val >> 24) & 0xff); + jazzio_writew(opaque, addr, val & 0xffff); + jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff); } =20 -static CPUReadMemoryFunc *int_read[3] =3D { - int_readb, - int_readw, - int_readl, +static CPUReadMemoryFunc *jazzio_read[3] =3D { + jazzio_readb, + jazzio_readw, + jazzio_readl, }; =20 -static CPUWriteMemoryFunc *int_write[3] =3D { - int_writeb, - int_writew, - int_writel, +static CPUWriteMemoryFunc *jazzio_write[3] =3D { + jazzio_writeb, + jazzio_writew, + jazzio_writel, }; =20 -#define G364_512KB_RAM (0x0) -#define G364_2MB_RAM (0x1) -#define G364_8MB_RAM (0x2) -#define G364_32MB_RAM (0x3) - static void rc4030_reset(void *opaque) { rc4030State *s =3D opaque; int i; =20 - s->config =3D (G364_2MB_RAM << 8) | 0x04; + s->config =3D 0x104; s->invalid_address_register =3D 0; =20 memset(s->dma_regs, 0, sizeof(s->dma_regs)); @@ -568,7 +587,6 @@ s->cache_ptag =3D s->cache_ltag =3D 0; s->cache_bmask =3D s->cache_bwin =3D 0; =20 - s->offset208 =3D 0; s->offset210 =3D 0x18186; s->nvram_protect =3D 7; s->offset238 =3D 7; @@ -577,21 +595,101 @@ s->imr_jazz =3D s->isr_jazz =3D 0; =20 s->itr =3D 0; - s->dummy32 =3D 0; =20 qemu_irq_lower(s->timer_irq); qemu_irq_lower(s->jazz_bus_irq); } =20 -qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus) +static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, in= t is_write) { + rc4030State *s =3D opaque; + target_phys_addr_t addr; + dma_pagetable_entry entry; + uint32_t offset; + + /* XXX: return errors to the caller? */ + + /* Check DMA channel consistency */ + if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE)) return; + if (is_write && (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DE= V)) return; + if (!is_write && !(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_= DEV)) return; + if (len > s->dma_regs[n][DMA_REG_COUNT]) len =3D s->dma_regs[n][DMA_= REG_COUNT]; + + /* Get DMA translation table entry */ + offset =3D (s->dma_regs[n][DMA_REG_ADDRESS] / DMA_PAGESIZE) * sizeof= (dma_pagetable_entry); + if (offset + sizeof(dma_pagetable_entry) > s->dma_tl_limit) return; + addr =3D (target_phys_addr_t)s->dma_tl_base + offset; + cpu_memory_rw_debug(cpu_single_env, addr, (uint8_t *)&entry, sizeof(= dma_pagetable_entry), 0); + + /* Read/write data at right place */ + addr =3D entry.frame + (s->dma_regs[n][DMA_REG_ADDRESS] & (DMA_PAGES= IZE - 1)); + cpu_physical_memory_rw(addr, buf, len, is_write); + s->dma_regs[n][DMA_REG_COUNT] -=3D len; + +#ifdef DEBUG_RC4030_DMA + { + int i; + if (is_write) + printf("rc4030 dma: Copying %d bytes from host %p to guest "= TARGET_FMT_lx "\n", + len, buf, addr); + else + printf("rc4030 dma: Copying %d bytes from guest " TARGET_FMT= _lx " to host %p\n", + len, addr, buf); + for (i =3D 0; i < len; i++) + printf("%c", isprint(buf[i]) ? buf[i] : '.'); + printf("\n"); + } +#endif +} + +struct rc4030DMAState { + void *opaque; + int n; +}; + +static void rc4030_dma_read(void *dma, uint8_t *buf, int len) +{ + rc4030_dma s =3D dma; + rc4030_do_dma(s->opaque, s->n, buf, len, 0); +} + +static void rc4030_dma_write(void *dma, uint8_t *buf, int len) +{ + rc4030_dma s =3D dma; + rc4030_do_dma(s->opaque, s->n, buf, len, 1); +} + +static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) +{ + rc4030_dma *s; + struct rc4030DMAState *p; + int i; + + s =3D (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n); + p =3D (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAS= tate) * n); + for (i =3D 0; i < n; i++) { + p->opaque =3D opaque; + p->n =3D i; + s[i] =3D p; + p++; + } + return s; +} + +qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, rc4030_dma **dm= as, + rc4030_dma_function *dma_read, rc4030_dma_function= *dma_write) +{ rc4030State *s; - int s_chipset, s_int; + int s_chipset, s_jazzio; =20 s =3D qemu_mallocz(sizeof(rc4030State)); if (!s) return NULL; =20 + *dmas =3D rc4030_allocate_dmas(s, 4); + *dma_read =3D rc4030_dma_read; + *dma_write =3D rc4030_dma_write; + s->periodic_timer =3D qemu_new_timer(vm_clock, rc4030_periodic_timer= , s); s->timer_irq =3D timer; s->jazz_bus_irq =3D jazz_bus; @@ -601,8 +699,8 @@ =20 s_chipset =3D cpu_register_io_memory(0, rc4030_read, rc4030_write, s= ); cpu_register_physical_memory(0x80000000, 0x300, s_chipset); - s_int =3D cpu_register_io_memory(0, int_read, int_write, s); - cpu_register_physical_memory(0xf0000000, 0x00001000, s_int); + s_jazzio =3D cpu_register_io_memory(0, jazzio_read, jazzio_write, s)= ; + cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio); =20 return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16); } --------------070603070001010708040502--