From: Richard Henderson <richard.henderson@linaro.org>
To: Jim MacArthur <jim.macarthur@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits
Date: Sat, 15 Nov 2025 13:21:44 +0100 [thread overview]
Message-ID: <492728c8-32f6-4e27-b879-e5f296eef8d3@linaro.org> (raw)
In-Reply-To: <20251112092048.450090-4-jim.macarthur@linaro.org>
On 11/12/25 10:17, Jim MacArthur wrote:
> + asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t"
> + : [x1] "=r" (idreg));
> + if ((idreg & 0xF00) == 0x100) {
This should be != 0, just like in isar_feature_aa64_asid2.
r~
next prev parent reply other threads:[~2025-11-15 12:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-12 9:17 [PATCH 0/3] Basic ASID2 support Jim MacArthur
2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
2025-11-15 12:12 ` Richard Henderson
2025-11-12 9:17 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur
2025-11-15 12:17 ` Richard Henderson
2025-11-12 9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
2025-11-15 12:21 ` Richard Henderson [this message]
-- strict thread matches above, loose matches on Subject: below --
2025-11-20 12:54 [PATCH v2 0/3] Basic ASID2 Support Jim MacArthur
2025-11-20 12:54 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
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