From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L5KSK-0002zP-8X for qemu-devel@nongnu.org; Wed, 26 Nov 2008 08:29:24 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L5KSE-0002wU-78 for qemu-devel@nongnu.org; Wed, 26 Nov 2008 08:29:20 -0500 Received: from [199.232.76.173] (port=46490 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L5KSC-0002vm-0k for qemu-devel@nongnu.org; Wed, 26 Nov 2008 08:29:16 -0500 Received: from mail.gmx.net ([213.165.64.20]:48000) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1L5KSA-0007Lk-MH for qemu-devel@nongnu.org; Wed, 26 Nov 2008 08:29:15 -0500 Message-ID: <492D4F27.1010709@gmx.net> Date: Wed, 26 Nov 2008 14:29:11 +0100 From: Carl-Daniel Hailfinger MIME-Version: 1.0 Subject: Re: [Qemu-devel] Modeling x86 early initialization accurately References: <492C80BF.4010103@gmx.net> <200811261137.56040.paul@codesourcery.com> In-Reply-To: <200811261137.56040.paul@codesourcery.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 26.11.2008 12:37, Paul Brook wrote: >> - Start up with all RAM being readonly. Writes should be discarded, >> reads will usually return 0xff or be undefined. The "undefined" variant >> would allow the code to allocate RAM once and just switch write access >> on/off. >> > > Does anything actually rely on this behavior? > No, but it would model hardware more closely. And it may be needed for a correct implementation of Suspend-to-RAM. > I can see the need to the other bits, but it seems kinda strange that anything > would rely on RAM being readonly. This seems more like a coreboot bug than > anything else. > coreboot doesn't rely on this. Once you use Suspend-to-RAM on x86, the need to avoid clobbering RAM contents during resume will strongly suggest this change. Alas, this is not important for my current goal of getting coreboot to run with actual i586 CPU code. Regards, Carl-Daniel -- http://www.hailfinger.org/