From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1L5mDK-0008IR-G2
	for qemu-devel@nongnu.org; Thu, 27 Nov 2008 14:07:46 -0500
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1L5mDI-0008H1-Hy
	for qemu-devel@nongnu.org; Thu, 27 Nov 2008 14:07:46 -0500
Received: from [199.232.76.173] (port=49473 helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1L5mDI-0008Gm-Cc
	for qemu-devel@nongnu.org; Thu, 27 Nov 2008 14:07:44 -0500
Received: from mail.gmx.net ([213.165.64.20]:43436)
	by monty-python.gnu.org with smtp (Exim 4.60)
	(envelope-from <c-d.hailfinger.devel.2006@gmx.net>)
	id 1L5mDH-0006JV-G7
	for qemu-devel@nongnu.org; Thu, 27 Nov 2008 14:07:44 -0500
Message-ID: <492EEFF8.50802@gmx.net>
Date: Thu, 27 Nov 2008 20:07:36 +0100
From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
MIME-Version: 1.0
Subject: Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for	S3
	ACPI state (suspend	to memory) in BIOS
References: <20081127110220.25353.83454.stgit@dhcp-1-237.tlv.redhat.com>	<492E8FCC.2020203@gmx.net>	<20081127123557.GB21985@redhat.com>
	<000301c950c2$4e2058b0$ea610a10$@com>
In-Reply-To: <000301c950c2$4e2058b0$ea610a10$@com>
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org
Cc: bochs-developers@lists.sourceforge.net, 'Gleb Natapov' <gleb@redhat.com>

On 27.11.2008 19:59, Stanislav wrote:
> In Bochs CPU doesn't have a cache memory emulated to use it as RAM but it is
> still possible to emulate cache-as-ram mode.
> The problem that cache-as-ram mode is very very very processor specific and
> implementation of it might be different between Intel and AMD for example.
> Which one to pick up ?
>   

I have worked on Intel, AMD and VIA implementations for Cache-as-RAM.
Avi Kivity suggested a simple algorithm which is a catchall for Intel
586, Intel Core 2 Duo, AMD K8, AMD K10 and VIA C7.

> Or might be better to invent some other mode especially for emulation
> reasons ?
>   

With the catchall emulation, inventing a special mode should be unneeded.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/