[Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Gleb Natapov]

Hello,

This patch series adds S3 (suspend to RAM) ACPI state to BIOS. Most
changes concern themselves with preventing BIOS from using memory
locations available to a guest OS.

Changelog:

v2:
- Don't disable SMM.
- Jump to resume vector ASAP. Don't execute entire POST.
- Use smp_cpus directly for smp initialization instead of special memory
  location.

v3:
- Stack pointer for rombios32 code depends on EBDA settings
- Fix .data and .rodata* section overlap
- Various small fixes

v4:
- If resume vector is NULL return to normal POST

v5:
- Call smm_init() at S3 resume boot
- Shadow BIOS before looking for resume vector

---

Gleb Natapov (5):
      Don't power down vga card on entering S3 state.
      Don't use unreserved memory in BIOS.
      Execute rombios32 code from rom address 0xe0000.
      Preserve memory content during SMM init.
      Add S3 state to DSDT. Handle resume event in the BIOS.


 bios/Makefile.in      |    1 
 bios/acpi-dsdt.dsl    |   45 +++++-
 bios/acpi-dsdt.hex    |  376 +++++++++++++++++++++++++------------------------
 bios/rombios.c        |   77 ++++++++--
 bios/rombios.h        |    1 
 bios/rombios32.c      |  132 ++++++++++++++---
 bios/rombios32.ld     |   10 +
 bios/rombios32start.S |   11 +
 8 files changed, 414 insertions(+), 239 deletions(-)

-- 
        Gleb.

[Qemu-devel] [PATCH v5 1/5] Add S3 state to DSDT. Handle resume event in the BIOS.

[Gleb Natapov]

Signed-off-by: Gleb Natapov <gleb@redhat.com>
---

 bios/acpi-dsdt.dsl |   30 +++++++++++---
 bios/acpi-dsdt.hex |   17 +++++---
 bios/rombios.c     |   51 ++++++++++++++++++++++++
 bios/rombios32.c   |  111 ++++++++++++++++++++++++++++++++++++++++++++++------
 4 files changed, 184 insertions(+), 25 deletions(-)

diff --git a/bios/acpi-dsdt.dsl b/bios/acpi-dsdt.dsl
index 19ac2f9..280a05e 100644
--- a/bios/acpi-dsdt.dsl
+++ b/bios/acpi-dsdt.dsl
@@ -531,11 +531,29 @@ DefinitionBlock (
         }
     }
 
-    /* S5 = power off state */
-    Name (_S5, Package (4) {
-        0x00, // PM1a_CNT.SLP_TYP
-        0x00, // PM2a_CNT.SLP_TYP
-        0x00, // reserved
-        0x00, // reserved
+    /*
+     * S3 (suspend-to-ram), S4 (suspend-to-disk) and S5 (power-off) type codes:
+     * must match piix4 emulation.
+     */
+    Name (\_S3, Package (0x04)
+    {
+        0x01,  /* PM1a_CNT.SLP_TYP */
+        0x01,  /* PM1b_CNT.SLP_TYP */
+        Zero,  /* reserved */
+        Zero   /* reserved */
+    })
+    Name (\_S4, Package (0x04)
+    {
+        Zero,  /* PM1a_CNT.SLP_TYP */
+        Zero,  /* PM1b_CNT.SLP_TYP */
+        Zero,  /* reserved */
+        Zero   /* reserved */
+    })
+    Name (\_S5, Package (0x04)
+    {
+        Zero,  /* PM1a_CNT.SLP_TYP */
+        Zero,  /* PM1b_CNT.SLP_TYP */
+        Zero,  /* reserved */
+        Zero   /* reserved */
     })
 }
diff --git a/bios/acpi-dsdt.hex b/bios/acpi-dsdt.hex
index 6bc6268..6088b18 100644
--- a/bios/acpi-dsdt.hex
+++ b/bios/acpi-dsdt.hex
@@ -1,22 +1,22 @@
 /*
  * 
  * Intel ACPI Component Architecture
- * ASL Optimizing Compiler version 20060912 [Nov 25 2006]
+ * ASL Optimizing Compiler version 20061109 [May 15 2007]
  * Copyright (C) 2000 - 2006 Intel Corporation
  * Supports ACPI Specification Revision 3.0a
  * 
- * Compilation of "acpi-dsdt.dsl" - Sun Sep 14 10:27:40 2008
+ * Compilation of "acpi-dsdt.dsl" - Mon Oct 27 10:37:05 2008
  * 
  * C source code output
  *
  */
-unsigned char AmlCode[] =
+const unsigned char AmlCode[] =
 {
-    0x44,0x53,0x44,0x54,0xC9,0x07,0x00,0x00,  /* 00000000    "DSDT...." */
-    0x01,0x0E,0x42,0x58,0x50,0x43,0x00,0x00,  /* 00000008    "..BXPC.." */
+    0x44,0x53,0x44,0x54,0xE1,0x07,0x00,0x00,  /* 00000000    "DSDT...." */
+    0x01,0x24,0x42,0x58,0x50,0x43,0x00,0x00,  /* 00000008    ".$BXPC.." */
     0x42,0x58,0x44,0x53,0x44,0x54,0x00,0x00,  /* 00000010    "BXDSDT.." */
     0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C,  /* 00000018    "....INTL" */
-    0x12,0x09,0x06,0x20,0x10,0x1C,0x5C,0x00,  /* 00000020    "... ..\." */
+    0x09,0x11,0x06,0x20,0x10,0x1C,0x5C,0x00,  /* 00000020    "... ..\." */
     0x5B,0x80,0x44,0x42,0x47,0x5F,0x01,0x0B,  /* 00000028    "[.DBG_.." */
     0x44,0xB0,0x0A,0x04,0x5B,0x81,0x0B,0x44,  /* 00000030    "D...[..D" */
     0x42,0x47,0x5F,0x03,0x44,0x42,0x47,0x4C,  /* 00000038    "BG_.DBGL" */
@@ -260,6 +260,9 @@ unsigned char AmlCode[] =
     0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F,0x82,  /* 000007A8    ".h.TMP_." */
     0x54,0x4D,0x50,0x5F,0x60,0x76,0x60,0x70,  /* 000007B0    "TMP_`v`p" */
     0x60,0x50,0x52,0x51,0x33,0x08,0x5F,0x53,  /* 000007B8    "`PRQ3._S" */
-    0x35,0x5F,0x12,0x06,0x04,0x00,0x00,0x00,  /* 000007C0    "5_......" */
+    0x33,0x5F,0x12,0x06,0x04,0x01,0x01,0x00,  /* 000007C0    "3_......" */
+    0x00,0x08,0x5F,0x53,0x34,0x5F,0x12,0x06,  /* 000007C8    ".._S4_.." */
+    0x04,0x00,0x00,0x00,0x00,0x08,0x5F,0x53,  /* 000007D0    "......_S" */
+    0x35,0x5F,0x12,0x06,0x04,0x00,0x00,0x00,  /* 000007D8    "5_......" */
     0x00,
 };
diff --git a/bios/rombios.c b/bios/rombios.c
index 9255b89..a34c6b2 100644
--- a/bios/rombios.c
+++ b/bios/rombios.c
@@ -1917,6 +1917,11 @@ shutdown_status_panic(status)
   BX_PANIC("Unimplemented shutdown status: %02x\n",(Bit8u)status);
 }
 
+void s3_resume_panic()
+{
+  BX_PANIC("Returned from s3_resume.\n");
+}
+
 //--------------------------------------------------------------------------
 // print_bios_banner
 //   displays a the bios version
@@ -2198,6 +2203,33 @@ debugger_off()
   outb(0xfedc, 0x00);
 }
 
+int
+s3_resume()
+{
+    Bit32u s3_wakeup_vector;
+    Bit8u s3_resume_flag;
+
+    s3_resume_flag = read_byte(0x40, 0xb0);
+    s3_wakeup_vector = read_dword(0x40, 0xb2);
+
+    BX_INFO("S3 resume called %x 0x%lx\n", s3_resume_flag, s3_wakeup_vector);
+    if (s3_resume_flag != 0xFE || !s3_wakeup_vector)
+	    return 0;
+
+    write_byte(0x40, 0xb0, 0);
+
+    /* setup wakeup vector */
+    write_word(0x40, 0xb6, (s3_wakeup_vector & 0xF)); /* IP */
+    write_word(0x40, 0xb8, (s3_wakeup_vector >> 4)); /* CS */
+
+    BX_INFO("S3 resume jump to %x:%x\n", (s3_wakeup_vector >> 4),
+		    (s3_wakeup_vector & 0xF));
+ASM_START
+    jmpf [0x04b6]
+ASM_END
+    return 1;
+}
+
 #if BX_USE_ATADRV
 
 // ---------------------------------------------------------------------------
@@ -9081,6 +9113,15 @@ retf_post_0x467:
   mov ss, [0x469]
   retf
 
+s3_post:
+#if BX_ROMBIOS32
+  call rombios32_init
+#endif
+  call _s3_resume
+  mov bl, #0x00
+  and ax, ax
+  jz normal_post
+  call _s3_resume_panic
 
 ;--------------------
 eoi_both_pics:
@@ -10005,6 +10046,10 @@ rombios32_05:
   ;; init the stack pointer
   mov esp, #0x00080000
 
+  ;; pass pointer to s3_resume_flag and s3_resume_vector to rombios32
+  push #0x04b0
+  push #0x04b2
+
   ;; call rombios32 code
   mov eax, #0x00040000
   call eax
@@ -10375,6 +10420,12 @@ normal_post:
   mov  ds, ax
   mov  ss, ax
 
+  ;; Save shutdown status
+  mov 0x04b0, bl
+
+  cmp bl, #0xfe
+  jz s3_post
+
   ;; zero out BIOS data area (40:00..40:ff)
   mov  es, ax
   mov  cx, #0x0080 ;; 128 words
diff --git a/bios/rombios32.c b/bios/rombios32.c
index 38cfe06..d9b59d5 100644
--- a/bios/rombios32.c
+++ b/bios/rombios32.c
@@ -180,6 +180,20 @@ void *memmove(void *d1, const void *s1, size_t len)
     return d1;
 }
 
+int memcmp(const void *s1, const void *s2, size_t len)
+{
+    const int8_t *p1 = s1;
+    const int8_t *p2 = s2;
+
+    while (len--) {
+        int r = *p1++ - *p2++;
+        if(r)
+            return r;
+    }
+
+    return 0;
+}
+
 size_t strlen(const char *s)
 {
     const char *s1;
@@ -625,7 +639,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
     return (irq_num + slot_addend) & 3;
 }
 
-static int find_bios_table_area(void)
+static void find_bios_table_area(void)
 {
     unsigned long addr;
     for(addr = 0xf0000; addr < 0x100000; addr += 16) {
@@ -634,17 +648,17 @@ static int find_bios_table_area(void)
             bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
             BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
                     bios_table_cur_addr, bios_table_end_addr);
-            return 0;
+            return;
         }
     }
-    return -1;
+    return;
 }
 
 static void bios_shadow_init(PCIDevice *d)
 {
     int v;
 
-    if (find_bios_table_area() < 0)
+    if (bios_table_cur_addr == 0)
         return;
 
     /* remap the BIOS to shadow RAM an keep it read/write while we
@@ -747,6 +761,18 @@ static void smm_init(PCIDevice *d)
 }
 #endif
 
+static void piix4_pm_enable(PCIDevice *d)
+{
+        /* PIIX4 Power Management device (for ACPI) */
+        pci_config_writel(d, 0x40, PM_IO_BASE | 1);
+        pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
+        pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
+        pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
+#ifdef BX_USE_SMM
+        smm_init(d);
+#endif
+}
+
 static void pci_bios_init_device(PCIDevice *d)
 {
     int class;
@@ -837,15 +863,9 @@ static void pci_bios_init_device(PCIDevice *d)
     if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
         /* PIIX4 Power Management device (for ACPI) */
         pm_io_base = PM_IO_BASE;
-        pci_config_writel(d, 0x40, pm_io_base | 1);
-        pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
         smb_io_base = SMB_IO_BASE;
-        pci_config_writel(d, 0x90, smb_io_base | 1);
-        pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
         pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
-#ifdef BX_USE_SMM
-        smm_init(d);
-#endif
+        piix4_pm_enable(d);
         acpi_enabled = 1;
     }
 }
@@ -1460,6 +1480,7 @@ void acpi_bios_init(void)
     memset(facs, 0, sizeof(*facs));
     memcpy(facs->signature, "FACS", 4);
     facs->length = cpu_to_le32(sizeof(*facs));
+    BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
 
     /* DSDT */
     memcpy(dsdt, AmlCode, sizeof(AmlCode));
@@ -2010,9 +2031,59 @@ void smbios_init(void)
     BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
 }
 
-void rombios32_init(void)
+static uint32_t find_resume_vector(void)
+{
+    unsigned long addr, start, end;
+
+#ifdef BX_USE_EBDA_TABLES
+    start = align(ebda_cur_addr, 16);
+    end = 0xa000 << 4;
+#else
+    if (bios_table_cur_addr == 0)
+        return 0;
+    start = align(bios_table_cur_addr, 16);
+    end = bios_table_end_addr;
+#endif
+
+    for (addr = start; addr < end; addr += 16) {
+        if (!memcmp((void*)addr, "RSD PTR ", 8)) {
+            struct rsdp_descriptor *rsdp = (void*)addr;
+            struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
+            struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
+            struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
+            return facs->firmware_waking_vector;
+        }
+    }
+
+    return 0;
+}
+
+static void find_440fx(PCIDevice *d)
+{
+    uint16_t vendor_id, device_id;
+
+    vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+    device_id = pci_config_readw(d, PCI_DEVICE_ID);
+
+    if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
+        i440_pcidev = *d;
+}
+
+static void reinit_piix4_pm(PCIDevice *d)
+{
+    uint16_t vendor_id, device_id;
+
+    vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+    device_id = pci_config_readw(d, PCI_DEVICE_ID);
+
+    if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
+        piix4_pm_enable(d);
+}
+
+void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
 {
     BX_INFO("Starting rombios32\n");
+    BX_INFO("Shutdown flag %x\n", *shutdown_flag);
 
 #ifdef BX_QEMU
     qemu_cfg_port = qemu_cfg_port_probe();
@@ -2024,6 +2095,22 @@ void rombios32_init(void)
 
     smp_probe();
 
+    find_bios_table_area();
+
+    if (*shutdown_flag == 0xfe) {
+        /* redirect bios read access to RAM */
+        pci_for_each_device(find_440fx);
+        bios_lock_shadow_ram(); /* bios is already copied */
+        *s3_resume_vector = find_resume_vector();
+        if (!*s3_resume_vector) {
+            BX_INFO("This is S3 resume but wakeup vector is NULL\n");
+        } else {
+            BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
+            pci_for_each_device(reinit_piix4_pm);
+        }
+        return;
+    }
+
     pci_bios_init();
 
     if (bios_table_cur_addr != 0) {

[Qemu-devel] [PATCH v5 2/5] Preserve memory content during SMM init.

[Gleb Natapov]

Signed-off-by: Gleb Natapov <gleb@redhat.com>
---

 bios/rombios32.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/bios/rombios32.c b/bios/rombios32.c
index d9b59d5..4093d88 100644
--- a/bios/rombios32.c
+++ b/bios/rombios32.c
@@ -731,6 +731,12 @@ static void smm_init(PCIDevice *d)
     value = pci_config_readl(d, 0x58);
     if ((value & (1 << 25)) == 0) {
 
+        /* enable the SMM memory window */
+        pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
+
+        /* save original memory content */
+        memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
+
         /* copy the SMM relocation code */
         memcpy((void *)0x38000, &smm_relocation_start,
                &smm_relocation_end - &smm_relocation_start);
@@ -747,8 +753,8 @@ static void smm_init(PCIDevice *d)
         /* wait until SMM code executed */
         while (inb(0xb3) != 0x00);
 
-        /* enable the SMM memory window */
-        pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
+        /* restore original memory content */
+        memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
 
         /* copy the SMM code */
         memcpy((void *)0xa8000, &smm_code_start,

[Qemu-devel] [PATCH v5 3/5] Execute rombios32 code from rom address 0xe0000.

[Gleb Natapov]

Signed-off-by: Gleb Natapov <gleb@redhat.com>
---

 bios/Makefile.in      |    1 +
 bios/rombios.c        |   17 +----------------
 bios/rombios32.ld     |   10 ++++------
 bios/rombios32start.S |    9 ++++++++-
 4 files changed, 14 insertions(+), 23 deletions(-)

diff --git a/bios/Makefile.in b/bios/Makefile.in
index b055910..af674b4 100644
--- a/bios/Makefile.in
+++ b/bios/Makefile.in
@@ -106,6 +106,7 @@ rombios32.o: rombios32.c acpi-dsdt.hex
 ifeq ("1", "0")
 acpi-dsdt.hex: acpi-dsdt.dsl
 	iasl -tc -p $@ $<
+	sed -i -e's/^unsigned/const unsigned/' $@
 endif
 
 rombios32start.o: rombios32start.S
diff --git a/bios/rombios.c b/bios/rombios.c
index a34c6b2..4e555a9 100644
--- a/bios/rombios.c
+++ b/bios/rombios.c
@@ -10036,13 +10036,6 @@ rombios32_05:
   mov gs, ax
   cld
 
-  ;; copy rombios32 code to ram (ram offset = 1MB)
-  mov esi, #0xfffe0000
-  mov edi, #0x00040000
-  mov ecx, #0x10000 / 4
-  rep
-    movsd
-
   ;; init the stack pointer
   mov esp, #0x00080000
 
@@ -10051,17 +10044,9 @@ rombios32_05:
   push #0x04b2
 
   ;; call rombios32 code
-  mov eax, #0x00040000
+  mov eax, #0x000e0000
   call eax
 
-  ;; reset the memory (some boot loaders such as syslinux suppose
-  ;; that the memory is set to zero)
-  mov edi, #0x00040000
-  mov ecx, #0x40000 / 4
-  xor eax, eax
-  rep
-    stosd
-
   ;; return to 16 bit protected mode first
   db 0xea
   dd rombios32_10
diff --git a/bios/rombios32.ld b/bios/rombios32.ld
index c7f6066..ff765c8 100644
--- a/bios/rombios32.ld
+++ b/bios/rombios32.ld
@@ -3,14 +3,12 @@ OUTPUT_ARCH(i386)
 ENTRY(_start);
 SECTIONS
 {
-        . = 0x00040000;
+        . = 0x000e0000;
         .text     : { *(.text)    }
-        .rodata    : { *(.rodata) }
-        . = ALIGN(4096);
-        .data     : { *(.data)    }
-        __bss_start = . ;
-        .bss      : { *(.bss) *(COMMON) }
+        .rodata    : { *(.rodata*) }
         _end = . ;
+        .data 0x700 : AT (_end) { __data_start = .; *(.data); __data_end = .;}
+        .bss      : { __bss_start = .; *(.bss) *(COMMON); __bss_end = .;}
         /DISCARD/ : { *(.stab)
                      *(.stabstr)
                      *(.comment)
diff --git a/bios/rombios32start.S b/bios/rombios32start.S
index 601e2b0..1900261 100644
--- a/bios/rombios32start.S
+++ b/bios/rombios32start.S
@@ -32,10 +32,17 @@ _start:
   /* clear bss section */
   xor %eax, %eax
   mov $__bss_start, %edi
-  mov $_end, %ecx
+  mov $__bss_end, %ecx
   sub %edi, %ecx
   rep stosb
 
+  /* copy data section */
+  mov $_end, %esi
+  mov $__data_start, %edi
+  mov $__data_end, %ecx
+  sub %edi, %ecx
+  rep movsb
+
   jmp rombios32_init
 
   .code16

[Qemu-devel] [PATCH v5 4/5] Don't use unreserved memory in BIOS.

[Gleb Natapov]

Use only first page and last page of low memory. OSes assumes that first
page is used by bios and last page is reserved in e820 map.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
---

 bios/rombios.c        |   11 +++++++----
 bios/rombios.h        |    1 -
 bios/rombios32.c      |   11 ++++-------
 bios/rombios32start.S |    2 +-
 4 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/bios/rombios.c b/bios/rombios.c
index 4e555a9..5a56716 100644
--- a/bios/rombios.c
+++ b/bios/rombios.c
@@ -4548,7 +4548,7 @@ ASM_END
                 {
                     case 0:
                         set_e820_range(ES, regs.u.r16.di,
-                                       0x0000000L, 0x0009fc00L, 1);
+                                       0x0000000L, 0x0009f000L, 1);
                         regs.u.r32.ebx = 1;
                         regs.u.r32.eax = 0x534D4150;
                         regs.u.r32.ecx = 0x14;
@@ -4557,7 +4557,7 @@ ASM_END
                         break;
                     case 1:
                         set_e820_range(ES, regs.u.r16.di,
-                                       0x0009fc00L, 0x000a0000L, 2);
+                                       0x0009f000L, 0x000a0000L, 2);
                         regs.u.r32.ebx = 2;
                         regs.u.r32.eax = 0x534D4150;
                         regs.u.r32.ecx = 0x14;
@@ -10036,8 +10036,11 @@ rombios32_05:
   mov gs, ax
   cld
 
-  ;; init the stack pointer
-  mov esp, #0x00080000
+  ;; init the stack pointer to point below EBDA
+  mov ax, [0x040e]
+  shl eax, #4
+  mov esp, #-0x10
+  add esp, eax
 
   ;; pass pointer to s3_resume_flag and s3_resume_vector to rombios32
   push #0x04b0
diff --git a/bios/rombios.h b/bios/rombios.h
index f0ed88e..b3df88b 100644
--- a/bios/rombios.h
+++ b/bios/rombios.h
@@ -56,7 +56,6 @@
 #define ACPI_DATA_SIZE    0x00010000L
 #define PM_IO_BASE        0xb000
 #define SMB_IO_BASE       0xb100
-#define CPU_COUNT_ADDR    0xf000
 
   // Define the application NAME
 #if defined(BX_QEMU)
diff --git a/bios/rombios32.c b/bios/rombios32.c
index 4093d88..1d8e0a3 100644
--- a/bios/rombios32.c
+++ b/bios/rombios32.c
@@ -57,7 +57,7 @@ typedef unsigned long long uint64_t;
 
 #define APIC_ENABLED 0x0100
 
-#define AP_BOOT_ADDR 0x10000
+#define AP_BOOT_ADDR 0x9f000
 
 #define MPTABLE_MAX_SIZE  0x00002000
 #define SMI_CMD_IO_ADDR   0xb2
@@ -392,7 +392,7 @@ void delay_ms(int n)
     }
 }
 
-int smp_cpus;
+uint16_t smp_cpus;
 uint32_t cpuid_signature;
 uint32_t cpuid_features;
 uint32_t cpuid_ext_features;
@@ -495,7 +495,7 @@ void smp_probe(void)
 {
     uint32_t val, sipi_vector;
 
-    smp_cpus = 1;
+    writew(&smp_cpus, 1);
     if (cpuid_features & CPUID_APIC) {
 
         /* enable local APIC */
@@ -503,7 +503,6 @@ void smp_probe(void)
         val |= APIC_ENABLED;
         writel(APIC_BASE + APIC_SVR, val);
 
-        writew((void *)CPU_COUNT_ADDR, 1);
         /* copy AP boot code */
         memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
                &smp_ap_boot_code_end - &smp_ap_boot_code_start);
@@ -514,10 +513,8 @@ void smp_probe(void)
         writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
         delay_ms(10);
-
-        smp_cpus = readw((void *)CPU_COUNT_ADDR);
     }
-    BX_INFO("Found %d cpu(s)\n", smp_cpus);
+    BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
 }
 
 /****************************************************/
diff --git a/bios/rombios32start.S b/bios/rombios32start.S
index 1900261..836652c 100644
--- a/bios/rombios32start.S
+++ b/bios/rombios32start.S
@@ -49,7 +49,7 @@ _start:
 smp_ap_boot_code_start:
   xor %ax, %ax
   mov %ax, %ds
-  lock incw CPU_COUNT_ADDR
+  lock incw smp_cpus
 1:
   hlt
   jmp 1b

[Qemu-devel] [PATCH v5 5/5] Don't power down vga card on entering S3 state.

[Gleb Natapov]

This is needed to fool windows to enter S3. The trick works for XP and
Windows2003, but Vista still refuse to allow S3.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
---

 bios/acpi-dsdt.dsl |   15 ++
 bios/acpi-dsdt.hex |  373 ++++++++++++++++++++++++++--------------------------
 2 files changed, 204 insertions(+), 184 deletions(-)

diff --git a/bios/acpi-dsdt.dsl b/bios/acpi-dsdt.dsl
index 280a05e..5fc3636 100644
--- a/bios/acpi-dsdt.dsl
+++ b/bios/acpi-dsdt.dsl
@@ -133,6 +133,21 @@ DefinitionBlock (
     }
 
     Scope(\_SB.PCI0) {
+        Device (VGA) {
+                 Name (_ADR, 0x00020000)
+                 Method (_S1D, 0, NotSerialized)
+                 {
+                         Return (0x00)
+                 }
+                 Method (_S2D, 0, NotSerialized)
+                 {
+                         Return (0x00)
+                 }
+                 Method (_S3D, 0, NotSerialized)
+                 {
+                         Return (0x00)
+                 }
+        }
 
 	/* PIIX3 ISA bridge */
         Device (ISA) {
diff --git a/bios/acpi-dsdt.hex b/bios/acpi-dsdt.hex
index 6088b18..a4c64e6 100644
--- a/bios/acpi-dsdt.hex
+++ b/bios/acpi-dsdt.hex
@@ -5,15 +5,15 @@
  * Copyright (C) 2000 - 2006 Intel Corporation
  * Supports ACPI Specification Revision 3.0a
  * 
- * Compilation of "acpi-dsdt.dsl" - Mon Oct 27 10:37:05 2008
+ * Compilation of "acpi-dsdt.dsl" - Mon Oct 27 10:39:43 2008
  * 
  * C source code output
  *
  */
 const unsigned char AmlCode[] =
 {
-    0x44,0x53,0x44,0x54,0xE1,0x07,0x00,0x00,  /* 00000000    "DSDT...." */
-    0x01,0x24,0x42,0x58,0x50,0x43,0x00,0x00,  /* 00000008    ".$BXPC.." */
+    0x44,0x53,0x44,0x54,0x0D,0x08,0x00,0x00,  /* 00000000    "DSDT...." */
+    0x01,0xA1,0x42,0x58,0x50,0x43,0x00,0x00,  /* 00000008    "..BXPC.." */
     0x42,0x58,0x44,0x53,0x44,0x54,0x00,0x00,  /* 00000010    "BXDSDT.." */
     0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C,  /* 00000018    "....INTL" */
     0x09,0x11,0x06,0x20,0x10,0x1C,0x5C,0x00,  /* 00000020    "... ..\." */
@@ -83,186 +83,191 @@ const unsigned char AmlCode[] =
     0x17,0x00,0x00,0x0C,0x01,0x00,0x00,0x00,  /* 00000220    "........" */
     0x00,0x00,0x00,0x00,0xE0,0xFF,0xFF,0xBF,  /* 00000228    "........" */
     0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,  /* 00000230    "........" */
-    0x1E,0x79,0x00,0x10,0x41,0x29,0x2E,0x5F,  /* 00000238    ".y..A)._" */
+    0x1E,0x79,0x00,0x10,0x4D,0x2B,0x2E,0x5F,  /* 00000238    ".y..M+._" */
     0x53,0x42,0x5F,0x50,0x43,0x49,0x30,0x5B,  /* 00000240    "SB_PCI0[" */
-    0x82,0x42,0x23,0x49,0x53,0x41,0x5F,0x08,  /* 00000248    ".B#ISA_." */
-    0x5F,0x41,0x44,0x52,0x0C,0x00,0x00,0x01,  /* 00000250    "_ADR...." */
-    0x00,0x5B,0x80,0x50,0x34,0x30,0x43,0x02,  /* 00000258    ".[.P40C." */
-    0x0A,0x60,0x0A,0x04,0x5B,0x82,0x2D,0x52,  /* 00000260    ".`..[.-R" */
-    0x54,0x43,0x5F,0x08,0x5F,0x48,0x49,0x44,  /* 00000268    "TC_._HID" */
-    0x0C,0x41,0xD0,0x0B,0x00,0x08,0x5F,0x43,  /* 00000270    ".A...._C" */
-    0x52,0x53,0x11,0x18,0x0A,0x15,0x47,0x01,  /* 00000278    "RS....G." */
-    0x70,0x00,0x70,0x00,0x10,0x02,0x22,0x00,  /* 00000280    "p.p..."." */
-    0x01,0x47,0x01,0x72,0x00,0x72,0x00,0x02,  /* 00000288    ".G.r.r.." */
-    0x06,0x79,0x00,0x5B,0x82,0x44,0x04,0x4B,  /* 00000290    ".y.[.D.K" */
-    0x42,0x44,0x5F,0x08,0x5F,0x48,0x49,0x44,  /* 00000298    "BD_._HID" */
-    0x0C,0x41,0xD0,0x03,0x03,0x14,0x09,0x5F,  /* 000002A0    ".A....._" */
-    0x53,0x54,0x41,0x00,0xA4,0x0A,0x0F,0x14,  /* 000002A8    "STA....." */
-    0x29,0x5F,0x43,0x52,0x53,0x00,0x08,0x54,  /* 000002B0    ")_CRS..T" */
-    0x4D,0x50,0x5F,0x11,0x18,0x0A,0x15,0x47,  /* 000002B8    "MP_....G" */
-    0x01,0x60,0x00,0x60,0x00,0x01,0x01,0x47,  /* 000002C0    ".`.`...G" */
-    0x01,0x64,0x00,0x64,0x00,0x01,0x01,0x22,  /* 000002C8    ".d.d..."" */
-    0x02,0x00,0x79,0x00,0xA4,0x54,0x4D,0x50,  /* 000002D0    "..y..TMP" */
-    0x5F,0x5B,0x82,0x33,0x4D,0x4F,0x55,0x5F,  /* 000002D8    "_[.3MOU_" */
-    0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,  /* 000002E0    "._HID.A." */
-    0x0F,0x13,0x14,0x09,0x5F,0x53,0x54,0x41,  /* 000002E8    "...._STA" */
-    0x00,0xA4,0x0A,0x0F,0x14,0x19,0x5F,0x43,  /* 000002F0    "......_C" */
-    0x52,0x53,0x00,0x08,0x54,0x4D,0x50,0x5F,  /* 000002F8    "RS..TMP_" */
-    0x11,0x08,0x0A,0x05,0x22,0x00,0x10,0x79,  /* 00000300    "...."..y" */
-    0x00,0xA4,0x54,0x4D,0x50,0x5F,0x5B,0x82,  /* 00000308    "..TMP_[." */
-    0x47,0x04,0x46,0x44,0x43,0x30,0x08,0x5F,  /* 00000310    "G.FDC0._" */
-    0x48,0x49,0x44,0x0C,0x41,0xD0,0x07,0x00,  /* 00000318    "HID.A..." */
-    0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,  /* 00000320    ".._STA.." */
-    0x0A,0x0F,0x14,0x2C,0x5F,0x43,0x52,0x53,  /* 00000328    "...,_CRS" */
-    0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x1B,  /* 00000330    "..BUF0.." */
-    0x0A,0x18,0x47,0x01,0xF2,0x03,0xF2,0x03,  /* 00000338    "..G....." */
-    0x00,0x04,0x47,0x01,0xF7,0x03,0xF7,0x03,  /* 00000340    "..G....." */
-    0x00,0x01,0x22,0x40,0x00,0x2A,0x04,0x00,  /* 00000348    ".."@.*.." */
-    0x79,0x00,0xA4,0x42,0x55,0x46,0x30,0x5B,  /* 00000350    "y..BUF0[" */
-    0x82,0x4B,0x05,0x4C,0x50,0x54,0x5F,0x08,  /* 00000358    ".K.LPT_." */
-    0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x04,  /* 00000360    "_HID.A.." */
-    0x00,0x14,0x28,0x5F,0x53,0x54,0x41,0x00,  /* 00000368    "..(_STA." */
-    0x70,0x5E,0x5E,0x5E,0x2E,0x50,0x58,0x31,  /* 00000370    "p^^^.PX1" */
-    0x33,0x44,0x52,0x53,0x41,0x60,0x7B,0x60,  /* 00000378    "3DRSA`{`" */
-    0x0C,0x00,0x00,0x00,0x80,0x60,0xA0,0x06,  /* 00000380    ".....`.." */
-    0x93,0x60,0x00,0xA4,0x00,0xA1,0x04,0xA4,  /* 00000388    ".`......" */
-    0x0A,0x0F,0x14,0x21,0x5F,0x43,0x52,0x53,  /* 00000390    "...!_CRS" */
-    0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x10,  /* 00000398    "..BUF0.." */
-    0x0A,0x0D,0x47,0x01,0x78,0x03,0x78,0x03,  /* 000003A0    "..G.x.x." */
-    0x08,0x08,0x22,0x80,0x00,0x79,0x00,0xA4,  /* 000003A8    ".."..y.." */
-    0x42,0x55,0x46,0x30,0x5B,0x82,0x41,0x06,  /* 000003B0    "BUF0[.A." */
-    0x43,0x4F,0x4D,0x31,0x08,0x5F,0x48,0x49,  /* 000003B8    "COM1._HI" */
-    0x44,0x0C,0x41,0xD0,0x05,0x01,0x08,0x5F,  /* 000003C0    "D.A...._" */
-    0x55,0x49,0x44,0x01,0x14,0x28,0x5F,0x53,  /* 000003C8    "UID..(_S" */
-    0x54,0x41,0x00,0x70,0x5E,0x5E,0x5E,0x2E,  /* 000003D0    "TA.p^^^." */
-    0x50,0x58,0x31,0x33,0x44,0x52,0x53,0x43,  /* 000003D8    "PX13DRSC" */
-    0x60,0x7B,0x60,0x0C,0x00,0x00,0x00,0x08,  /* 000003E0    "`{`....." */
-    0x60,0xA0,0x06,0x93,0x60,0x00,0xA4,0x00,  /* 000003E8    "`...`..." */
-    0xA1,0x04,0xA4,0x0A,0x0F,0x14,0x21,0x5F,  /* 000003F0    "......!_" */
-    0x43,0x52,0x53,0x00,0x08,0x42,0x55,0x46,  /* 000003F8    "CRS..BUF" */
-    0x30,0x11,0x10,0x0A,0x0D,0x47,0x01,0xF8,  /* 00000400    "0....G.." */
-    0x03,0xF8,0x03,0x00,0x08,0x22,0x10,0x00,  /* 00000408    ".....".." */
-    0x79,0x00,0xA4,0x42,0x55,0x46,0x30,0x5B,  /* 00000410    "y..BUF0[" */
-    0x82,0x42,0x06,0x43,0x4F,0x4D,0x32,0x08,  /* 00000418    ".B.COM2." */
-    0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x05,  /* 00000420    "_HID.A.." */
-    0x01,0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,  /* 00000428    ".._UID.." */
-    0x14,0x28,0x5F,0x53,0x54,0x41,0x00,0x70,  /* 00000430    ".(_STA.p" */
-    0x5E,0x5E,0x5E,0x2E,0x50,0x58,0x31,0x33,  /* 00000438    "^^^.PX13" */
-    0x44,0x52,0x53,0x43,0x60,0x7B,0x60,0x0C,  /* 00000440    "DRSC`{`." */
-    0x00,0x00,0x00,0x80,0x60,0xA0,0x06,0x93,  /* 00000448    "....`..." */
-    0x60,0x00,0xA4,0x00,0xA1,0x04,0xA4,0x0A,  /* 00000450    "`......." */
-    0x0F,0x14,0x21,0x5F,0x43,0x52,0x53,0x00,  /* 00000458    "..!_CRS." */
-    0x08,0x42,0x55,0x46,0x30,0x11,0x10,0x0A,  /* 00000460    ".BUF0..." */
-    0x0D,0x47,0x01,0xF8,0x02,0xF8,0x02,0x00,  /* 00000468    ".G......" */
-    0x08,0x22,0x08,0x00,0x79,0x00,0xA4,0x42,  /* 00000470    "."..y..B" */
-    0x55,0x46,0x30,0x5B,0x82,0x40,0x05,0x50,  /* 00000478    "UF0[.@.P" */
-    0x58,0x31,0x33,0x08,0x5F,0x41,0x44,0x52,  /* 00000480    "X13._ADR" */
-    0x0C,0x03,0x00,0x01,0x00,0x5B,0x80,0x50,  /* 00000488    ".....[.P" */
-    0x31,0x33,0x43,0x02,0x0A,0x5C,0x0A,0x24,  /* 00000490    "13C..\.$" */
-    0x5B,0x81,0x33,0x50,0x31,0x33,0x43,0x03,  /* 00000498    "[.3P13C." */
-    0x44,0x52,0x53,0x41,0x20,0x44,0x52,0x53,  /* 000004A0    "DRSA DRS" */
-    0x42,0x20,0x44,0x52,0x53,0x43,0x20,0x44,  /* 000004A8    "B DRSC D" */
-    0x52,0x53,0x45,0x20,0x44,0x52,0x53,0x46,  /* 000004B0    "RSE DRSF" */
-    0x20,0x44,0x52,0x53,0x47,0x20,0x44,0x52,  /* 000004B8    " DRSG DR" */
-    0x53,0x48,0x20,0x44,0x52,0x53,0x49,0x20,  /* 000004C0    "SH DRSI " */
-    0x44,0x52,0x53,0x4A,0x20,0x10,0x4F,0x2E,  /* 000004C8    "DRSJ .O." */
-    0x5F,0x53,0x42,0x5F,0x5B,0x81,0x24,0x2F,  /* 000004D0    "_SB_[.$/" */
-    0x03,0x50,0x43,0x49,0x30,0x49,0x53,0x41,  /* 000004D8    ".PCI0ISA" */
-    0x5F,0x50,0x34,0x30,0x43,0x01,0x50,0x52,  /* 000004E0    "_P40C.PR" */
-    0x51,0x30,0x08,0x50,0x52,0x51,0x31,0x08,  /* 000004E8    "Q0.PRQ1." */
-    0x50,0x52,0x51,0x32,0x08,0x50,0x52,0x51,  /* 000004F0    "PRQ2.PRQ" */
-    0x33,0x08,0x5B,0x82,0x4E,0x0A,0x4C,0x4E,  /* 000004F8    "3.[.N.LN" */
-    0x4B,0x41,0x08,0x5F,0x48,0x49,0x44,0x0C,  /* 00000500    "KA._HID." */
-    0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55,0x49,  /* 00000508    "A...._UI" */
-    0x44,0x01,0x08,0x5F,0x50,0x52,0x53,0x11,  /* 00000510    "D.._PRS." */
-    0x09,0x0A,0x06,0x23,0xF8,0x1E,0x18,0x79,  /* 00000518    "...#...y" */
-    0x00,0x14,0x1A,0x5F,0x53,0x54,0x41,0x00,  /* 00000520    "..._STA." */
-    0x70,0x0A,0x0B,0x60,0xA0,0x0D,0x7B,0x0A,  /* 00000528    "p..`..{." */
-    0x80,0x50,0x52,0x51,0x30,0x61,0x70,0x0A,  /* 00000530    ".PRQ0ap." */
-    0x09,0x60,0xA4,0x60,0x14,0x11,0x5F,0x44,  /* 00000538    ".`.`.._D" */
-    0x49,0x53,0x00,0x7D,0x50,0x52,0x51,0x30,  /* 00000540    "IS.}PRQ0" */
-    0x0A,0x80,0x50,0x52,0x51,0x30,0x14,0x3F,  /* 00000548    "..PRQ0.?" */
-    0x5F,0x43,0x52,0x53,0x00,0x08,0x50,0x52,  /* 00000550    "_CRS..PR" */
-    0x52,0x30,0x11,0x09,0x0A,0x06,0x23,0x02,  /* 00000558    "R0....#." */
-    0x00,0x18,0x79,0x00,0x8B,0x50,0x52,0x52,  /* 00000560    "..y..PRR" */
-    0x30,0x01,0x54,0x4D,0x50,0x5F,0x70,0x50,  /* 00000568    "0.TMP_pP" */
-    0x52,0x51,0x30,0x60,0xA0,0x0C,0x95,0x60,  /* 00000570    "RQ0`...`" */
-    0x0A,0x80,0x79,0x01,0x60,0x54,0x4D,0x50,  /* 00000578    "..y.`TMP" */
-    0x5F,0xA1,0x07,0x70,0x00,0x54,0x4D,0x50,  /* 00000580    "_..p.TMP" */
-    0x5F,0xA4,0x50,0x52,0x52,0x30,0x14,0x1B,  /* 00000588    "_.PRR0.." */
-    0x5F,0x53,0x52,0x53,0x01,0x8B,0x68,0x01,  /* 00000590    "_SRS..h." */
-    0x54,0x4D,0x50,0x5F,0x82,0x54,0x4D,0x50,  /* 00000598    "TMP_.TMP" */
-    0x5F,0x60,0x76,0x60,0x70,0x60,0x50,0x52,  /* 000005A0    "_`v`p`PR" */
-    0x51,0x30,0x5B,0x82,0x4F,0x0A,0x4C,0x4E,  /* 000005A8    "Q0[.O.LN" */
-    0x4B,0x42,0x08,0x5F,0x48,0x49,0x44,0x0C,  /* 000005B0    "KB._HID." */
-    0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55,0x49,  /* 000005B8    "A...._UI" */
-    0x44,0x0A,0x02,0x08,0x5F,0x50,0x52,0x53,  /* 000005C0    "D..._PRS" */
-    0x11,0x09,0x0A,0x06,0x23,0xF8,0x1E,0x18,  /* 000005C8    "....#..." */
-    0x79,0x00,0x14,0x1A,0x5F,0x53,0x54,0x41,  /* 000005D0    "y..._STA" */
-    0x00,0x70,0x0A,0x0B,0x60,0xA0,0x0D,0x7B,  /* 000005D8    ".p..`..{" */
-    0x0A,0x80,0x50,0x52,0x51,0x31,0x61,0x70,  /* 000005E0    "..PRQ1ap" */
-    0x0A,0x09,0x60,0xA4,0x60,0x14,0x11,0x5F,  /* 000005E8    "..`.`.._" */
-    0x44,0x49,0x53,0x00,0x7D,0x50,0x52,0x51,  /* 000005F0    "DIS.}PRQ" */
-    0x31,0x0A,0x80,0x50,0x52,0x51,0x31,0x14,  /* 000005F8    "1..PRQ1." */
-    0x3F,0x5F,0x43,0x52,0x53,0x00,0x08,0x50,  /* 00000600    "?_CRS..P" */
-    0x52,0x52,0x30,0x11,0x09,0x0A,0x06,0x23,  /* 00000608    "RR0....#" */
-    0x02,0x00,0x18,0x79,0x00,0x8B,0x50,0x52,  /* 00000610    "...y..PR" */
-    0x52,0x30,0x01,0x54,0x4D,0x50,0x5F,0x70,  /* 00000618    "R0.TMP_p" */
-    0x50,0x52,0x51,0x31,0x60,0xA0,0x0C,0x95,  /* 00000620    "PRQ1`..." */
-    0x60,0x0A,0x80,0x79,0x01,0x60,0x54,0x4D,  /* 00000628    "`..y.`TM" */
-    0x50,0x5F,0xA1,0x07,0x70,0x00,0x54,0x4D,  /* 00000630    "P_..p.TM" */
-    0x50,0x5F,0xA4,0x50,0x52,0x52,0x30,0x14,  /* 00000638    "P_.PRR0." */
-    0x1B,0x5F,0x53,0x52,0x53,0x01,0x8B,0x68,  /* 00000640    "._SRS..h" */
-    0x01,0x54,0x4D,0x50,0x5F,0x82,0x54,0x4D,  /* 00000648    ".TMP_.TM" */
-    0x50,0x5F,0x60,0x76,0x60,0x70,0x60,0x50,  /* 00000650    "P_`v`p`P" */
-    0x52,0x51,0x31,0x5B,0x82,0x4F,0x0A,0x4C,  /* 00000658    "RQ1[.O.L" */
-    0x4E,0x4B,0x43,0x08,0x5F,0x48,0x49,0x44,  /* 00000660    "NKC._HID" */
-    0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55,  /* 00000668    ".A...._U" */
-    0x49,0x44,0x0A,0x03,0x08,0x5F,0x50,0x52,  /* 00000670    "ID..._PR" */
-    0x53,0x11,0x09,0x0A,0x06,0x23,0xF8,0x1E,  /* 00000678    "S....#.." */
-    0x18,0x79,0x00,0x14,0x1A,0x5F,0x53,0x54,  /* 00000680    ".y..._ST" */
-    0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0,0x0D,  /* 00000688    "A.p..`.." */
-    0x7B,0x0A,0x80,0x50,0x52,0x51,0x32,0x61,  /* 00000690    "{..PRQ2a" */
-    0x70,0x0A,0x09,0x60,0xA4,0x60,0x14,0x11,  /* 00000698    "p..`.`.." */
-    0x5F,0x44,0x49,0x53,0x00,0x7D,0x50,0x52,  /* 000006A0    "_DIS.}PR" */
-    0x51,0x32,0x0A,0x80,0x50,0x52,0x51,0x32,  /* 000006A8    "Q2..PRQ2" */
-    0x14,0x3F,0x5F,0x43,0x52,0x53,0x00,0x08,  /* 000006B0    ".?_CRS.." */
-    0x50,0x52,0x52,0x30,0x11,0x09,0x0A,0x06,  /* 000006B8    "PRR0...." */
-    0x23,0x02,0x00,0x18,0x79,0x00,0x8B,0x50,  /* 000006C0    "#...y..P" */
-    0x52,0x52,0x30,0x01,0x54,0x4D,0x50,0x5F,  /* 000006C8    "RR0.TMP_" */
-    0x70,0x50,0x52,0x51,0x32,0x60,0xA0,0x0C,  /* 000006D0    "pPRQ2`.." */
-    0x95,0x60,0x0A,0x80,0x79,0x01,0x60,0x54,  /* 000006D8    ".`..y.`T" */
-    0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00,0x54,  /* 000006E0    "MP_..p.T" */
-    0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52,0x30,  /* 000006E8    "MP_.PRR0" */
-    0x14,0x1B,0x5F,0x53,0x52,0x53,0x01,0x8B,  /* 000006F0    ".._SRS.." */
-    0x68,0x01,0x54,0x4D,0x50,0x5F,0x82,0x54,  /* 000006F8    "h.TMP_.T" */
-    0x4D,0x50,0x5F,0x60,0x76,0x60,0x70,0x60,  /* 00000700    "MP_`v`p`" */
-    0x50,0x52,0x51,0x32,0x5B,0x82,0x4F,0x0A,  /* 00000708    "PRQ2[.O." */
-    0x4C,0x4E,0x4B,0x44,0x08,0x5F,0x48,0x49,  /* 00000710    "LNKD._HI" */
-    0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,  /* 00000718    "D.A...._" */
-    0x55,0x49,0x44,0x0A,0x04,0x08,0x5F,0x50,  /* 00000720    "UID..._P" */
-    0x52,0x53,0x11,0x09,0x0A,0x06,0x23,0xF8,  /* 00000728    "RS....#." */
-    0x1E,0x18,0x79,0x00,0x14,0x1A,0x5F,0x53,  /* 00000730    "..y..._S" */
-    0x54,0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0,  /* 00000738    "TA.p..`." */
-    0x0D,0x7B,0x0A,0x80,0x50,0x52,0x51,0x33,  /* 00000740    ".{..PRQ3" */
-    0x61,0x70,0x0A,0x09,0x60,0xA4,0x60,0x14,  /* 00000748    "ap..`.`." */
-    0x11,0x5F,0x44,0x49,0x53,0x00,0x7D,0x50,  /* 00000750    "._DIS.}P" */
-    0x52,0x51,0x33,0x0A,0x80,0x50,0x52,0x51,  /* 00000758    "RQ3..PRQ" */
-    0x33,0x14,0x3F,0x5F,0x43,0x52,0x53,0x00,  /* 00000760    "3.?_CRS." */
-    0x08,0x50,0x52,0x52,0x30,0x11,0x09,0x0A,  /* 00000768    ".PRR0..." */
-    0x06,0x23,0x02,0x00,0x18,0x79,0x00,0x8B,  /* 00000770    ".#...y.." */
-    0x50,0x52,0x52,0x30,0x01,0x54,0x4D,0x50,  /* 00000778    "PRR0.TMP" */
-    0x5F,0x70,0x50,0x52,0x51,0x33,0x60,0xA0,  /* 00000780    "_pPRQ3`." */
-    0x0C,0x95,0x60,0x0A,0x80,0x79,0x01,0x60,  /* 00000788    "..`..y.`" */
-    0x54,0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00,  /* 00000790    "TMP_..p." */
-    0x54,0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52,  /* 00000798    "TMP_.PRR" */
-    0x30,0x14,0x1B,0x5F,0x53,0x52,0x53,0x01,  /* 000007A0    "0.._SRS." */
-    0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F,0x82,  /* 000007A8    ".h.TMP_." */
-    0x54,0x4D,0x50,0x5F,0x60,0x76,0x60,0x70,  /* 000007B0    "TMP_`v`p" */
-    0x60,0x50,0x52,0x51,0x33,0x08,0x5F,0x53,  /* 000007B8    "`PRQ3._S" */
-    0x33,0x5F,0x12,0x06,0x04,0x01,0x01,0x00,  /* 000007C0    "3_......" */
-    0x00,0x08,0x5F,0x53,0x34,0x5F,0x12,0x06,  /* 000007C8    ".._S4_.." */
-    0x04,0x00,0x00,0x00,0x00,0x08,0x5F,0x53,  /* 000007D0    "......_S" */
-    0x35,0x5F,0x12,0x06,0x04,0x00,0x00,0x00,  /* 000007D8    "5_......" */
-    0x00,
+    0x82,0x2A,0x56,0x47,0x41,0x5F,0x08,0x5F,  /* 00000248    ".*VGA_._" */
+    0x41,0x44,0x52,0x0C,0x00,0x00,0x02,0x00,  /* 00000250    "ADR....." */
+    0x14,0x08,0x5F,0x53,0x31,0x44,0x00,0xA4,  /* 00000258    ".._S1D.." */
+    0x00,0x14,0x08,0x5F,0x53,0x32,0x44,0x00,  /* 00000260    "..._S2D." */
+    0xA4,0x00,0x14,0x08,0x5F,0x53,0x33,0x44,  /* 00000268    "...._S3D" */
+    0x00,0xA4,0x00,0x5B,0x82,0x42,0x23,0x49,  /* 00000270    "...[.B#I" */
+    0x53,0x41,0x5F,0x08,0x5F,0x41,0x44,0x52,  /* 00000278    "SA_._ADR" */
+    0x0C,0x00,0x00,0x01,0x00,0x5B,0x80,0x50,  /* 00000280    ".....[.P" */
+    0x34,0x30,0x43,0x02,0x0A,0x60,0x0A,0x04,  /* 00000288    "40C..`.." */
+    0x5B,0x82,0x2D,0x52,0x54,0x43,0x5F,0x08,  /* 00000290    "[.-RTC_." */
+    0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x0B,  /* 00000298    "_HID.A.." */
+    0x00,0x08,0x5F,0x43,0x52,0x53,0x11,0x18,  /* 000002A0    ".._CRS.." */
+    0x0A,0x15,0x47,0x01,0x70,0x00,0x70,0x00,  /* 000002A8    "..G.p.p." */
+    0x10,0x02,0x22,0x00,0x01,0x47,0x01,0x72,  /* 000002B0    ".."..G.r" */
+    0x00,0x72,0x00,0x02,0x06,0x79,0x00,0x5B,  /* 000002B8    ".r...y.[" */
+    0x82,0x44,0x04,0x4B,0x42,0x44,0x5F,0x08,  /* 000002C0    ".D.KBD_." */
+    0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x03,  /* 000002C8    "_HID.A.." */
+    0x03,0x14,0x09,0x5F,0x53,0x54,0x41,0x00,  /* 000002D0    "..._STA." */
+    0xA4,0x0A,0x0F,0x14,0x29,0x5F,0x43,0x52,  /* 000002D8    "....)_CR" */
+    0x53,0x00,0x08,0x54,0x4D,0x50,0x5F,0x11,  /* 000002E0    "S..TMP_." */
+    0x18,0x0A,0x15,0x47,0x01,0x60,0x00,0x60,  /* 000002E8    "...G.`.`" */
+    0x00,0x01,0x01,0x47,0x01,0x64,0x00,0x64,  /* 000002F0    "...G.d.d" */
+    0x00,0x01,0x01,0x22,0x02,0x00,0x79,0x00,  /* 000002F8    "..."..y." */
+    0xA4,0x54,0x4D,0x50,0x5F,0x5B,0x82,0x33,  /* 00000300    ".TMP_[.3" */
+    0x4D,0x4F,0x55,0x5F,0x08,0x5F,0x48,0x49,  /* 00000308    "MOU_._HI" */
+    0x44,0x0C,0x41,0xD0,0x0F,0x13,0x14,0x09,  /* 00000310    "D.A....." */
+    0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,0x0F,  /* 00000318    "_STA...." */
+    0x14,0x19,0x5F,0x43,0x52,0x53,0x00,0x08,  /* 00000320    ".._CRS.." */
+    0x54,0x4D,0x50,0x5F,0x11,0x08,0x0A,0x05,  /* 00000328    "TMP_...." */
+    0x22,0x00,0x10,0x79,0x00,0xA4,0x54,0x4D,  /* 00000330    ""..y..TM" */
+    0x50,0x5F,0x5B,0x82,0x47,0x04,0x46,0x44,  /* 00000338    "P_[.G.FD" */
+    0x43,0x30,0x08,0x5F,0x48,0x49,0x44,0x0C,  /* 00000340    "C0._HID." */
+    0x41,0xD0,0x07,0x00,0x14,0x09,0x5F,0x53,  /* 00000348    "A....._S" */
+    0x54,0x41,0x00,0xA4,0x0A,0x0F,0x14,0x2C,  /* 00000350    "TA.....," */
+    0x5F,0x43,0x52,0x53,0x00,0x08,0x42,0x55,  /* 00000358    "_CRS..BU" */
+    0x46,0x30,0x11,0x1B,0x0A,0x18,0x47,0x01,  /* 00000360    "F0....G." */
+    0xF2,0x03,0xF2,0x03,0x00,0x04,0x47,0x01,  /* 00000368    "......G." */
+    0xF7,0x03,0xF7,0x03,0x00,0x01,0x22,0x40,  /* 00000370    "......"@" */
+    0x00,0x2A,0x04,0x00,0x79,0x00,0xA4,0x42,  /* 00000378    ".*..y..B" */
+    0x55,0x46,0x30,0x5B,0x82,0x4B,0x05,0x4C,  /* 00000380    "UF0[.K.L" */
+    0x50,0x54,0x5F,0x08,0x5F,0x48,0x49,0x44,  /* 00000388    "PT_._HID" */
+    0x0C,0x41,0xD0,0x04,0x00,0x14,0x28,0x5F,  /* 00000390    ".A....(_" */
+    0x53,0x54,0x41,0x00,0x70,0x5E,0x5E,0x5E,  /* 00000398    "STA.p^^^" */
+    0x2E,0x50,0x58,0x31,0x33,0x44,0x52,0x53,  /* 000003A0    ".PX13DRS" */
+    0x41,0x60,0x7B,0x60,0x0C,0x00,0x00,0x00,  /* 000003A8    "A`{`...." */
+    0x80,0x60,0xA0,0x06,0x93,0x60,0x00,0xA4,  /* 000003B0    ".`...`.." */
+    0x00,0xA1,0x04,0xA4,0x0A,0x0F,0x14,0x21,  /* 000003B8    ".......!" */
+    0x5F,0x43,0x52,0x53,0x00,0x08,0x42,0x55,  /* 000003C0    "_CRS..BU" */
+    0x46,0x30,0x11,0x10,0x0A,0x0D,0x47,0x01,  /* 000003C8    "F0....G." */
+    0x78,0x03,0x78,0x03,0x08,0x08,0x22,0x80,  /* 000003D0    "x.x..."." */
+    0x00,0x79,0x00,0xA4,0x42,0x55,0x46,0x30,  /* 000003D8    ".y..BUF0" */
+    0x5B,0x82,0x41,0x06,0x43,0x4F,0x4D,0x31,  /* 000003E0    "[.A.COM1" */
+    0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,  /* 000003E8    "._HID.A." */
+    0x05,0x01,0x08,0x5F,0x55,0x49,0x44,0x01,  /* 000003F0    "..._UID." */
+    0x14,0x28,0x5F,0x53,0x54,0x41,0x00,0x70,  /* 000003F8    ".(_STA.p" */
+    0x5E,0x5E,0x5E,0x2E,0x50,0x58,0x31,0x33,  /* 00000400    "^^^.PX13" */
+    0x44,0x52,0x53,0x43,0x60,0x7B,0x60,0x0C,  /* 00000408    "DRSC`{`." */
+    0x00,0x00,0x00,0x08,0x60,0xA0,0x06,0x93,  /* 00000410    "....`..." */
+    0x60,0x00,0xA4,0x00,0xA1,0x04,0xA4,0x0A,  /* 00000418    "`......." */
+    0x0F,0x14,0x21,0x5F,0x43,0x52,0x53,0x00,  /* 00000420    "..!_CRS." */
+    0x08,0x42,0x55,0x46,0x30,0x11,0x10,0x0A,  /* 00000428    ".BUF0..." */
+    0x0D,0x47,0x01,0xF8,0x03,0xF8,0x03,0x00,  /* 00000430    ".G......" */
+    0x08,0x22,0x10,0x00,0x79,0x00,0xA4,0x42,  /* 00000438    "."..y..B" */
+    0x55,0x46,0x30,0x5B,0x82,0x42,0x06,0x43,  /* 00000440    "UF0[.B.C" */
+    0x4F,0x4D,0x32,0x08,0x5F,0x48,0x49,0x44,  /* 00000448    "OM2._HID" */
+    0x0C,0x41,0xD0,0x05,0x01,0x08,0x5F,0x55,  /* 00000450    ".A...._U" */
+    0x49,0x44,0x0A,0x02,0x14,0x28,0x5F,0x53,  /* 00000458    "ID...(_S" */
+    0x54,0x41,0x00,0x70,0x5E,0x5E,0x5E,0x2E,  /* 00000460    "TA.p^^^." */
+    0x50,0x58,0x31,0x33,0x44,0x52,0x53,0x43,  /* 00000468    "PX13DRSC" */
+    0x60,0x7B,0x60,0x0C,0x00,0x00,0x00,0x80,  /* 00000470    "`{`....." */
+    0x60,0xA0,0x06,0x93,0x60,0x00,0xA4,0x00,  /* 00000478    "`...`..." */
+    0xA1,0x04,0xA4,0x0A,0x0F,0x14,0x21,0x5F,  /* 00000480    "......!_" */
+    0x43,0x52,0x53,0x00,0x08,0x42,0x55,0x46,  /* 00000488    "CRS..BUF" */
+    0x30,0x11,0x10,0x0A,0x0D,0x47,0x01,0xF8,  /* 00000490    "0....G.." */
+    0x02,0xF8,0x02,0x00,0x08,0x22,0x08,0x00,  /* 00000498    ".....".." */
+    0x79,0x00,0xA4,0x42,0x55,0x46,0x30,0x5B,  /* 000004A0    "y..BUF0[" */
+    0x82,0x40,0x05,0x50,0x58,0x31,0x33,0x08,  /* 000004A8    ".@.PX13." */
+    0x5F,0x41,0x44,0x52,0x0C,0x03,0x00,0x01,  /* 000004B0    "_ADR...." */
+    0x00,0x5B,0x80,0x50,0x31,0x33,0x43,0x02,  /* 000004B8    ".[.P13C." */
+    0x0A,0x5C,0x0A,0x24,0x5B,0x81,0x33,0x50,  /* 000004C0    ".\.$[.3P" */
+    0x31,0x33,0x43,0x03,0x44,0x52,0x53,0x41,  /* 000004C8    "13C.DRSA" */
+    0x20,0x44,0x52,0x53,0x42,0x20,0x44,0x52,  /* 000004D0    " DRSB DR" */
+    0x53,0x43,0x20,0x44,0x52,0x53,0x45,0x20,  /* 000004D8    "SC DRSE " */
+    0x44,0x52,0x53,0x46,0x20,0x44,0x52,0x53,  /* 000004E0    "DRSF DRS" */
+    0x47,0x20,0x44,0x52,0x53,0x48,0x20,0x44,  /* 000004E8    "G DRSH D" */
+    0x52,0x53,0x49,0x20,0x44,0x52,0x53,0x4A,  /* 000004F0    "RSI DRSJ" */
+    0x20,0x10,0x4F,0x2E,0x5F,0x53,0x42,0x5F,  /* 000004F8    " .O._SB_" */
+    0x5B,0x81,0x24,0x2F,0x03,0x50,0x43,0x49,  /* 00000500    "[.$/.PCI" */
+    0x30,0x49,0x53,0x41,0x5F,0x50,0x34,0x30,  /* 00000508    "0ISA_P40" */
+    0x43,0x01,0x50,0x52,0x51,0x30,0x08,0x50,  /* 00000510    "C.PRQ0.P" */
+    0x52,0x51,0x31,0x08,0x50,0x52,0x51,0x32,  /* 00000518    "RQ1.PRQ2" */
+    0x08,0x50,0x52,0x51,0x33,0x08,0x5B,0x82,  /* 00000520    ".PRQ3.[." */
+    0x4E,0x0A,0x4C,0x4E,0x4B,0x41,0x08,0x5F,  /* 00000528    "N.LNKA._" */
+    0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,  /* 00000530    "HID.A..." */
+    0x08,0x5F,0x55,0x49,0x44,0x01,0x08,0x5F,  /* 00000538    "._UID.._" */
+    0x50,0x52,0x53,0x11,0x09,0x0A,0x06,0x23,  /* 00000540    "PRS....#" */
+    0xF8,0x1E,0x18,0x79,0x00,0x14,0x1A,0x5F,  /* 00000548    "...y..._" */
+    0x53,0x54,0x41,0x00,0x70,0x0A,0x0B,0x60,  /* 00000550    "STA.p..`" */
+    0xA0,0x0D,0x7B,0x0A,0x80,0x50,0x52,0x51,  /* 00000558    "..{..PRQ" */
+    0x30,0x61,0x70,0x0A,0x09,0x60,0xA4,0x60,  /* 00000560    "0ap..`.`" */
+    0x14,0x11,0x5F,0x44,0x49,0x53,0x00,0x7D,  /* 00000568    ".._DIS.}" */
+    0x50,0x52,0x51,0x30,0x0A,0x80,0x50,0x52,  /* 00000570    "PRQ0..PR" */
+    0x51,0x30,0x14,0x3F,0x5F,0x43,0x52,0x53,  /* 00000578    "Q0.?_CRS" */
+    0x00,0x08,0x50,0x52,0x52,0x30,0x11,0x09,  /* 00000580    "..PRR0.." */
+    0x0A,0x06,0x23,0x02,0x00,0x18,0x79,0x00,  /* 00000588    "..#...y." */
+    0x8B,0x50,0x52,0x52,0x30,0x01,0x54,0x4D,  /* 00000590    ".PRR0.TM" */
+    0x50,0x5F,0x70,0x50,0x52,0x51,0x30,0x60,  /* 00000598    "P_pPRQ0`" */
+    0xA0,0x0C,0x95,0x60,0x0A,0x80,0x79,0x01,  /* 000005A0    "...`..y." */
+    0x60,0x54,0x4D,0x50,0x5F,0xA1,0x07,0x70,  /* 000005A8    "`TMP_..p" */
+    0x00,0x54,0x4D,0x50,0x5F,0xA4,0x50,0x52,  /* 000005B0    ".TMP_.PR" */
+    0x52,0x30,0x14,0x1B,0x5F,0x53,0x52,0x53,  /* 000005B8    "R0.._SRS" */
+    0x01,0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F,  /* 000005C0    "..h.TMP_" */
+    0x82,0x54,0x4D,0x50,0x5F,0x60,0x76,0x60,  /* 000005C8    ".TMP_`v`" */
+    0x70,0x60,0x50,0x52,0x51,0x30,0x5B,0x82,  /* 000005D0    "p`PRQ0[." */
+    0x4F,0x0A,0x4C,0x4E,0x4B,0x42,0x08,0x5F,  /* 000005D8    "O.LNKB._" */
+    0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,  /* 000005E0    "HID.A..." */
+    0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,0x08,  /* 000005E8    "._UID..." */
+    0x5F,0x50,0x52,0x53,0x11,0x09,0x0A,0x06,  /* 000005F0    "_PRS...." */
+    0x23,0xF8,0x1E,0x18,0x79,0x00,0x14,0x1A,  /* 000005F8    "#...y..." */
+    0x5F,0x53,0x54,0x41,0x00,0x70,0x0A,0x0B,  /* 00000600    "_STA.p.." */
+    0x60,0xA0,0x0D,0x7B,0x0A,0x80,0x50,0x52,  /* 00000608    "`..{..PR" */
+    0x51,0x31,0x61,0x70,0x0A,0x09,0x60,0xA4,  /* 00000610    "Q1ap..`." */
+    0x60,0x14,0x11,0x5F,0x44,0x49,0x53,0x00,  /* 00000618    "`.._DIS." */
+    0x7D,0x50,0x52,0x51,0x31,0x0A,0x80,0x50,  /* 00000620    "}PRQ1..P" */
+    0x52,0x51,0x31,0x14,0x3F,0x5F,0x43,0x52,  /* 00000628    "RQ1.?_CR" */
+    0x53,0x00,0x08,0x50,0x52,0x52,0x30,0x11,  /* 00000630    "S..PRR0." */
+    0x09,0x0A,0x06,0x23,0x02,0x00,0x18,0x79,  /* 00000638    "...#...y" */
+    0x00,0x8B,0x50,0x52,0x52,0x30,0x01,0x54,  /* 00000640    "..PRR0.T" */
+    0x4D,0x50,0x5F,0x70,0x50,0x52,0x51,0x31,  /* 00000648    "MP_pPRQ1" */
+    0x60,0xA0,0x0C,0x95,0x60,0x0A,0x80,0x79,  /* 00000650    "`...`..y" */
+    0x01,0x60,0x54,0x4D,0x50,0x5F,0xA1,0x07,  /* 00000658    ".`TMP_.." */
+    0x70,0x00,0x54,0x4D,0x50,0x5F,0xA4,0x50,  /* 00000660    "p.TMP_.P" */
+    0x52,0x52,0x30,0x14,0x1B,0x5F,0x53,0x52,  /* 00000668    "RR0.._SR" */
+    0x53,0x01,0x8B,0x68,0x01,0x54,0x4D,0x50,  /* 00000670    "S..h.TMP" */
+    0x5F,0x82,0x54,0x4D,0x50,0x5F,0x60,0x76,  /* 00000678    "_.TMP_`v" */
+    0x60,0x70,0x60,0x50,0x52,0x51,0x31,0x5B,  /* 00000680    "`p`PRQ1[" */
+    0x82,0x4F,0x0A,0x4C,0x4E,0x4B,0x43,0x08,  /* 00000688    ".O.LNKC." */
+    0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,  /* 00000690    "_HID.A.." */
+    0x0F,0x08,0x5F,0x55,0x49,0x44,0x0A,0x03,  /* 00000698    ".._UID.." */
+    0x08,0x5F,0x50,0x52,0x53,0x11,0x09,0x0A,  /* 000006A0    "._PRS..." */
+    0x06,0x23,0xF8,0x1E,0x18,0x79,0x00,0x14,  /* 000006A8    ".#...y.." */
+    0x1A,0x5F,0x53,0x54,0x41,0x00,0x70,0x0A,  /* 000006B0    "._STA.p." */
+    0x0B,0x60,0xA0,0x0D,0x7B,0x0A,0x80,0x50,  /* 000006B8    ".`..{..P" */
+    0x52,0x51,0x32,0x61,0x70,0x0A,0x09,0x60,  /* 000006C0    "RQ2ap..`" */
+    0xA4,0x60,0x14,0x11,0x5F,0x44,0x49,0x53,  /* 000006C8    ".`.._DIS" */
+    0x00,0x7D,0x50,0x52,0x51,0x32,0x0A,0x80,  /* 000006D0    ".}PRQ2.." */
+    0x50,0x52,0x51,0x32,0x14,0x3F,0x5F,0x43,  /* 000006D8    "PRQ2.?_C" */
+    0x52,0x53,0x00,0x08,0x50,0x52,0x52,0x30,  /* 000006E0    "RS..PRR0" */
+    0x11,0x09,0x0A,0x06,0x23,0x02,0x00,0x18,  /* 000006E8    "....#..." */
+    0x79,0x00,0x8B,0x50,0x52,0x52,0x30,0x01,  /* 000006F0    "y..PRR0." */
+    0x54,0x4D,0x50,0x5F,0x70,0x50,0x52,0x51,  /* 000006F8    "TMP_pPRQ" */
+    0x32,0x60,0xA0,0x0C,0x95,0x60,0x0A,0x80,  /* 00000700    "2`...`.." */
+    0x79,0x01,0x60,0x54,0x4D,0x50,0x5F,0xA1,  /* 00000708    "y.`TMP_." */
+    0x07,0x70,0x00,0x54,0x4D,0x50,0x5F,0xA4,  /* 00000710    ".p.TMP_." */
+    0x50,0x52,0x52,0x30,0x14,0x1B,0x5F,0x53,  /* 00000718    "PRR0.._S" */
+    0x52,0x53,0x01,0x8B,0x68,0x01,0x54,0x4D,  /* 00000720    "RS..h.TM" */
+    0x50,0x5F,0x82,0x54,0x4D,0x50,0x5F,0x60,  /* 00000728    "P_.TMP_`" */
+    0x76,0x60,0x70,0x60,0x50,0x52,0x51,0x32,  /* 00000730    "v`p`PRQ2" */
+    0x5B,0x82,0x4F,0x0A,0x4C,0x4E,0x4B,0x44,  /* 00000738    "[.O.LNKD" */
+    0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,  /* 00000740    "._HID.A." */
+    0x0C,0x0F,0x08,0x5F,0x55,0x49,0x44,0x0A,  /* 00000748    "..._UID." */
+    0x04,0x08,0x5F,0x50,0x52,0x53,0x11,0x09,  /* 00000750    ".._PRS.." */
+    0x0A,0x06,0x23,0xF8,0x1E,0x18,0x79,0x00,  /* 00000758    "..#...y." */
+    0x14,0x1A,0x5F,0x53,0x54,0x41,0x00,0x70,  /* 00000760    ".._STA.p" */
+    0x0A,0x0B,0x60,0xA0,0x0D,0x7B,0x0A,0x80,  /* 00000768    "..`..{.." */
+    0x50,0x52,0x51,0x33,0x61,0x70,0x0A,0x09,  /* 00000770    "PRQ3ap.." */
+    0x60,0xA4,0x60,0x14,0x11,0x5F,0x44,0x49,  /* 00000778    "`.`.._DI" */
+    0x53,0x00,0x7D,0x50,0x52,0x51,0x33,0x0A,  /* 00000780    "S.}PRQ3." */
+    0x80,0x50,0x52,0x51,0x33,0x14,0x3F,0x5F,  /* 00000788    ".PRQ3.?_" */
+    0x43,0x52,0x53,0x00,0x08,0x50,0x52,0x52,  /* 00000790    "CRS..PRR" */
+    0x30,0x11,0x09,0x0A,0x06,0x23,0x02,0x00,  /* 00000798    "0....#.." */
+    0x18,0x79,0x00,0x8B,0x50,0x52,0x52,0x30,  /* 000007A0    ".y..PRR0" */
+    0x01,0x54,0x4D,0x50,0x5F,0x70,0x50,0x52,  /* 000007A8    ".TMP_pPR" */
+    0x51,0x33,0x60,0xA0,0x0C,0x95,0x60,0x0A,  /* 000007B0    "Q3`...`." */
+    0x80,0x79,0x01,0x60,0x54,0x4D,0x50,0x5F,  /* 000007B8    ".y.`TMP_" */
+    0xA1,0x07,0x70,0x00,0x54,0x4D,0x50,0x5F,  /* 000007C0    "..p.TMP_" */
+    0xA4,0x50,0x52,0x52,0x30,0x14,0x1B,0x5F,  /* 000007C8    ".PRR0.._" */
+    0x53,0x52,0x53,0x01,0x8B,0x68,0x01,0x54,  /* 000007D0    "SRS..h.T" */
+    0x4D,0x50,0x5F,0x82,0x54,0x4D,0x50,0x5F,  /* 000007D8    "MP_.TMP_" */
+    0x60,0x76,0x60,0x70,0x60,0x50,0x52,0x51,  /* 000007E0    "`v`p`PRQ" */
+    0x33,0x08,0x5F,0x53,0x33,0x5F,0x12,0x06,  /* 000007E8    "3._S3_.." */
+    0x04,0x01,0x01,0x00,0x00,0x08,0x5F,0x53,  /* 000007F0    "......_S" */
+    0x34,0x5F,0x12,0x06,0x04,0x00,0x00,0x00,  /* 000007F8    "4_......" */
+    0x00,0x08,0x5F,0x53,0x35,0x5F,0x12,0x06,  /* 00000800    ".._S5_.." */
+    0x04,0x00,0x00,0x00,0x00,
 };

Re: [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Carl-Daniel Hailfinger]

Hi,

On 27.11.2008 12:02, Gleb Natapov wrote:
> This patch series adds S3 (suspend to RAM) ACPI state to BIOS. Most
> changes concern themselves with preventing BIOS from using memory
> locations available to a guest OS.
>   

I see the problem you're facing with the overwrite and it looks there
might be a cleaner solution: If you can lock the CPU cache so that
writes don't get passed through to RAM, you're free to use any area
(with a few contraints) for stack without having to worry about
clobbering memory contents there.

That method is called Cache-as-RAM and I'm currently trying to implement
it in Qemu. I haven't looked into Bochs yet, but it should be doable
there as well.

coreboot (a free x86 firmware/BIOS replacement) is using Cache-as-RAM
and I believe quite a few commercial BIOSes use that technique as well.

Regards,
Carl-Daniel

Re: [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Gleb Natapov]

On Thu, Nov 27, 2008 at 01:17:16PM +0100, Carl-Daniel Hailfinger wrote:
> Hi,
> 
> On 27.11.2008 12:02, Gleb Natapov wrote:
> > This patch series adds S3 (suspend to RAM) ACPI state to BIOS. Most
> > changes concern themselves with preventing BIOS from using memory
> > locations available to a guest OS.
> >   
> 
> I see the problem you're facing with the overwrite and it looks there
> might be a cleaner solution: If you can lock the CPU cache so that
> writes don't get passed through to RAM, you're free to use any area
> (with a few contraints) for stack without having to worry about
> clobbering memory contents there.
> 
> That method is called Cache-as-RAM and I'm currently trying to implement
> it in Qemu. I haven't looked into Bochs yet, but it should be doable
> there as well.
> 
It would be nice to not worry about stack location. We may try to use it
when you changes will work in Qemu and BOCHS.

--
			Gleb.

RE: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Stanislav]

In Bochs CPU doesn't have a cache memory emulated to use it as RAM but it is
still possible to emulate cache-as-ram mode.
The problem that cache-as-ram mode is very very very processor specific and
implementation of it might be different between Intel and AMD for example.
Which one to pick up ?
Or might be better to invent some other mode especially for emulation
reasons ?

Stanislav

-----Original Message-----
From: Gleb Natapov [mailto:gleb@redhat.com] 
Sent: Thursday, November 27, 2008 2:36 PM
To: qemu-devel@nongnu.org
Cc: bochs-developers@lists.sourceforge.net
Subject: Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3
ACPI state (suspend to memory) in BIOS

On Thu, Nov 27, 2008 at 01:17:16PM +0100, Carl-Daniel Hailfinger wrote:
> Hi,
> 
> On 27.11.2008 12:02, Gleb Natapov wrote:
> > This patch series adds S3 (suspend to RAM) ACPI state to BIOS. Most
> > changes concern themselves with preventing BIOS from using memory
> > locations available to a guest OS.
> >   
> 
> I see the problem you're facing with the overwrite and it looks there
> might be a cleaner solution: If you can lock the CPU cache so that
> writes don't get passed through to RAM, you're free to use any area
> (with a few contraints) for stack without having to worry about
> clobbering memory contents there.
> 
> That method is called Cache-as-RAM and I'm currently trying to implement
> it in Qemu. I haven't looked into Bochs yet, but it should be doable
> there as well.
> 
It would be nice to not worry about stack location. We may try to use it
when you changes will work in Qemu and BOCHS.

--
			Gleb.

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Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Carl-Daniel Hailfinger]

On 27.11.2008 19:59, Stanislav wrote:
> In Bochs CPU doesn't have a cache memory emulated to use it as RAM but it is
> still possible to emulate cache-as-ram mode.
> The problem that cache-as-ram mode is very very very processor specific and
> implementation of it might be different between Intel and AMD for example.
> Which one to pick up ?
>   

I have worked on Intel, AMD and VIA implementations for Cache-as-RAM.
Avi Kivity suggested a simple algorithm which is a catchall for Intel
586, Intel Core 2 Duo, AMD K8, AMD K10 and VIA C7.

> Or might be better to invent some other mode especially for emulation
> reasons ?
>   

With the catchall emulation, inventing a special mode should be unneeded.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

RE: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Stanislav]

What is the catchall emulation ? Could you explain/point me some docs ?

Thanks,
Stanislav

-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] 
Sent: Thursday, November 27, 2008 9:08 PM
To: qemu-devel@nongnu.org
Cc: bochs-developers@lists.sourceforge.net
Subject: Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3
ACPI state (suspend to memory) in BIOS

On 27.11.2008 19:59, Stanislav wrote:
> In Bochs CPU doesn't have a cache memory emulated to use it as RAM but it
is
> still possible to emulate cache-as-ram mode.
> The problem that cache-as-ram mode is very very very processor specific
and
> implementation of it might be different between Intel and AMD for example.
> Which one to pick up ?
>   

I have worked on Intel, AMD and VIA implementations for Cache-as-RAM.
Avi Kivity suggested a simple algorithm which is a catchall for Intel
586, Intel Core 2 Duo, AMD K8, AMD K10 and VIA C7.

> Or might be better to invent some other mode especially for emulation
> reasons ?
>   

With the catchall emulation, inventing a special mode should be unneeded.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/


-------------------------------------------------------------------------
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Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Carl-Daniel Hailfinger]

On 27.11.2008 21:04, Stanislav wrote:
> What is the catchall emulation ? Could you explain/point me some docs ?
>   

Sorry, it was only a brief sentence. Basically, if the total size of all
cached areas is not bigger than CPU cache size, no cache line will be
evicted and the cache behaves like Cache-as-RAM (CAR). That should be
doable in Bochs, KVM and Qemu.

Or were you looking for BIOS code to enable CAR? That is indeed
processor specific, but any of the existing CAR implementations will
work if the catchall emulation is used.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

RE: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Stanislav]

Again, I mean Bochs doesn't emulate caches. So what do you mean by catchall
emulation ?
To allocate kind of dummy 32K block and use it when CRAM mode and delete
immediately after ?
About the way you enable CRAM mode - it would be nice if we agree to use a
protocol which real hardware needs.
I still hope to be able to execute real hardware BIOSes on Bochs for example
...

Stanislav

-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] 
Sent: Thursday, November 27, 2008 11:05 PM
To: qemu-devel@nongnu.org
Cc: bochs-developers@lists.sourceforge.net
Subject: Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3
ACPI state (suspend to memory) in BIOS

On 27.11.2008 21:04, Stanislav wrote:
> What is the catchall emulation ? Could you explain/point me some docs ?
>   

Sorry, it was only a brief sentence. Basically, if the total size of all
cached areas is not bigger than CPU cache size, no cache line will be
evicted and the cache behaves like Cache-as-RAM (CAR). That should be
doable in Bochs, KVM and Qemu.

Or were you looking for BIOS code to enable CAR? That is indeed
processor specific, but any of the existing CAR implementations will
work if the catchall emulation is used.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/


-------------------------------------------------------------------------
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Build the coolest Linux based applications with Moblin SDK & win great
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Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS

[Carl-Daniel Hailfinger]

On 29.11.2008 20:42, Stanislav wrote:
> Again, I mean Bochs doesn't emulate caches. So what do you mean by catchall
> emulation ?
> To allocate kind of dummy 32K block and use it when CRAM mode and delete
> immediately after ?
>   

Yes, exactly. However, the size of the dummy block depends on your cache
size. And I have seen Intel CPUs (with 2 MB cache) which used up to 1056
kB of cache during CAR mode.

> About the way you enable CRAM mode - it would be nice if we agree to use a
> protocol which real hardware needs.
>   

Yes. That is my goal. The problem is that CPU documentation is often a
bit ambiguous about how CAR mode is enabled. AFAIK the common
denominator is the CARsize <= Cachesize setting. That is really unusual
for any point in time (during OS execution) except for the short time
where CAR is enabled in the firmware/BIOS.

> I still hope to be able to execute real hardware BIOSes on Bochs for example
>   

That would be cool. The RAM controller emulation may need some tweaking,
though.

Regards,
Carl-Daniel

> Stanislav
>
> -----Original Message-----
> From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] 
> Sent: Thursday, November 27, 2008 11:05 PM
> To: qemu-devel@nongnu.org
> Cc: bochs-developers@lists.sourceforge.net
> Subject: Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3
> ACPI state (suspend to memory) in BIOS
>
> On 27.11.2008 21:04, Stanislav wrote:
>   
>> What is the catchall emulation ? Could you explain/point me some docs ?
>>   
>>     
>
> Sorry, it was only a brief sentence. Basically, if the total size of all
> cached areas is not bigger than CPU cache size, no cache line will be
> evicted and the cache behaves like Cache-as-RAM (CAR). That should be
> doable in Bochs, KVM and Qemu.
>
> Or were you looking for BIOS code to enable CAR? That is indeed
> processor specific, but any of the existing CAR implementations will
> work if the catchall emulation is used.
>
> Regards,
> Carl-Daniel
>
>   


-- 
http://www.hailfinger.org/

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT. Handle resume event in the BIOS.

[Kevin O'Connor]

Hi Gleb,

On Thu, Nov 27, 2008 at 01:02:25PM +0200, Gleb Natapov wrote:
[...]
> @@ -10375,6 +10420,12 @@ normal_post:
>    mov  ds, ax
>    mov  ss, ax
>  
> +  ;; Save shutdown status
> +  mov 0x04b0, bl
> +
> +  cmp bl, #0xfe
> +  jz s3_post
> +

What sets 40:b0 to 0xfe on a resume?

Also, wouldn't this corrupt memory used by the stack (the stack gets
set to 0xfffe, and s3_post has call insns in it)?

-Kevin

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT. Handle resume event in the BIOS.

[Gleb Natapov]

On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
> Hi Gleb,
> 
> On Thu, Nov 27, 2008 at 01:02:25PM +0200, Gleb Natapov wrote:
> [...]
> > @@ -10375,6 +10420,12 @@ normal_post:
> >    mov  ds, ax
> >    mov  ss, ax
> >  
> > +  ;; Save shutdown status
> > +  mov 0x04b0, bl
> > +
> > +  cmp bl, #0xfe
> > +  jz s3_post
> > +
> 
> What sets 40:b0 to 0xfe on a resume?
> 
Qemu/Bochs.

> Also, wouldn't this corrupt memory used by the stack (the stack gets
> set to 0xfffe, and s3_post has call insns in it)?
> 

Oh. I thought it was set to be at the top of the first page, but it has
one extra 'f' :( We should change it to be 0xffe instead.

--
			Gleb.

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT. Handle resume event in the BIOS.

[Kevin O'Connor]

On Sun, Dec 07, 2008 at 11:20:31AM +0200, Gleb Natapov wrote:
> On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
> > On Thu, Nov 27, 2008 at 01:02:25PM +0200, Gleb Natapov wrote:
> > > +  ;; Save shutdown status
> > > +  mov 0x04b0, bl
> > > +
> > > +  cmp bl, #0xfe
> > > +  jz s3_post
> > What sets 40:b0 to 0xfe on a resume?
> Qemu/Bochs.

Thanks.

If we're going to set a flag to indicate a resume, I think we should
use more than one byte to ensure we don't invoke that path on random
memory.  (Maybe something like 0x5333524d -- 'S3RM'?)

Also, can the ACPI dsdt code set the flag instead of the emulators?

-Kevin

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT. Handle resume event in the BIOS.

[Gleb Natapov]

On Sun, Dec 07, 2008 at 10:10:44AM -0500, Kevin O'Connor wrote:
> On Sun, Dec 07, 2008 at 11:20:31AM +0200, Gleb Natapov wrote:
> > On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
> > > On Thu, Nov 27, 2008 at 01:02:25PM +0200, Gleb Natapov wrote:
> > > > +  ;; Save shutdown status
> > > > +  mov 0x04b0, bl
> > > > +
> > > > +  cmp bl, #0xfe
> > > > +  jz s3_post
> > > What sets 40:b0 to 0xfe on a resume?
> > Qemu/Bochs.
> 
> Thanks.
> 
> If we're going to set a flag to indicate a resume, I think we should
> use more than one byte to ensure we don't invoke that path on random
> memory.  (Maybe something like 0x5333524d -- 'S3RM'?)
> 
> Also, can the ACPI dsdt code set the flag instead of the emulators?
> 
Sorry I gave you a wrong answer. Qemu/BOCHS write 0xfe to CMOS offset
0xf (reboot reason) and BIOS saves it into 40:b0. We cannot write into
CMOS from AML since windows doesn't like it.

--

			Gleb.

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT. Handle resume event in the BIOS.

[Gleb Natapov]

On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
> Also, wouldn't this corrupt memory used by the stack (the stack gets
> set to 0xfffe, and s3_post has call insns in it)?
Here is the patch to set stack pointer to a different value on S3 resume:

Signed-off-by: Gleb Natapov <gleb@redhat.com>

diff --git a/bios/rombios.c b/bios/rombios.c
index 7a9c1fd..8e1d3ec 100644
--- a/bios/rombios.c
+++ b/bios/rombios.c
@@ -9114,6 +9114,7 @@ retf_post_0x467:
   retf
 
 s3_post:
+  mov sp, #0xffe
 #if BX_ROMBIOS32
   call rombios32_init
 #endif
--
			Gleb.

[Qemu-devel] RE: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT. Handle resume event in the BIOS.

[Stanislav]

Sebastian, Kevin, Let me know if any of the patches here should be
integrated to Bochs ...

 Stanislav

-----Original Message-----
From: Gleb Natapov [mailto:gleb@redhat.com] 
Sent: Tuesday, December 09, 2008 3:39 PM
To: bochs-developers@lists.sourceforge.net
Cc: Kevin O'Connor; qemu-devel@nongnu.org
Subject: Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT. Handle
resume event in the BIOS.

On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
> Also, wouldn't this corrupt memory used by the stack (the stack gets
> set to 0xfffe, and s3_post has call insns in it)?
Here is the patch to set stack pointer to a different value on S3 resume:

Signed-off-by: Gleb Natapov <gleb@redhat.com>

diff --git a/bios/rombios.c b/bios/rombios.c
index 7a9c1fd..8e1d3ec 100644
--- a/bios/rombios.c
+++ b/bios/rombios.c
@@ -9114,6 +9114,7 @@ retf_post_0x467:
   retf
 
 s3_post:
+  mov sp, #0xffe
 #if BX_ROMBIOS32
   call rombios32_init
 #endif
--
			Gleb.

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[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT.Handle resume event in the BIOS.

[Sebastian Herbszt]

Gleb Natapov wrote:
> On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
>> Hi Gleb,
>> 
>> On Thu, Nov 27, 2008 at 01:02:25PM +0200, Gleb Natapov wrote:
>> [...]
>> > @@ -10375,6 +10420,12 @@ normal_post:
>> >    mov  ds, ax
>> >    mov  ss, ax
>> >  
>> > +  ;; Save shutdown status
>> > +  mov 0x04b0, bl
>> > +
>> > +  cmp bl, #0xfe
>> > +  jz s3_post
>> > +
>> 
>> What sets 40:b0 to 0xfe on a resume?
>> 
> Qemu/Bochs.
> 
>> Also, wouldn't this corrupt memory used by the stack (the stack gets
>> set to 0xfffe, and s3_post has call insns in it)?

insns = instructions?

> Oh. I thought it was set to be at the top of the first page, but it has
> one extra 'f' :( We should change it to be 0xffe instead.

Can you please explain this memory corruption? Why would "this" (?) corrupt
memory used by the stack?

We set the stack to 0xfffe and then call rombios32_init. rombios32_init saves
the current ss:sp and then uses own stack, which is now located below the EBDA.
0xfffe is "user memory", same applys to 0xffe so in both cases we use "user memory".

Do you suggest 0xffe because it's in the first page (i assume 4KB pages) reserved for
BIOS use?

- Sebastian

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT.Handle resume event in the BIOS.

[Kevin O'Connor]

On Tue, Dec 09, 2008 at 11:26:53PM +0100, Sebastian Herbszt wrote:
> Gleb Natapov wrote:
> > On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
> >> Also, wouldn't this corrupt memory used by the stack (the stack gets
> >> set to 0xfffe, and s3_post has call insns in it)?
> > Oh. I thought it was set to be at the top of the first page, but it has
> > one extra 'f' :( We should change it to be 0xffe instead.
> 
> Can you please explain this memory corruption? Why would "this" (?) corrupt
> memory used by the stack?

On an s3 resume, memory the OS may be using must not be changed by the
bios.  When bochs bios detects an s3 resume, it jumps to s3_post with
the stack pointer set to 0xfffe.  In s3_post, there are "call"
instruction which will alter memory at 0xfffe (to store the return
address).  This could break the resume, because the OS could be using
that memory for something else.

Gleb is suggesting that we change that to 0xffe, because the OS can't
be using memory at that address and expect s3 resume to work.  (The
first 4KiB is reserved for BIOS use.)

-Kevin

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT.Handle resume event in the BIOS.

[Gleb Natapov]

On Tue, Dec 09, 2008 at 07:06:04PM -0500, Kevin O'Connor wrote:
> On Tue, Dec 09, 2008 at 11:26:53PM +0100, Sebastian Herbszt wrote:
> > Gleb Natapov wrote:
> > > On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
> > >> Also, wouldn't this corrupt memory used by the stack (the stack gets
> > >> set to 0xfffe, and s3_post has call insns in it)?
> > > Oh. I thought it was set to be at the top of the first page, but it has
> > > one extra 'f' :( We should change it to be 0xffe instead.
> > 
> > Can you please explain this memory corruption? Why would "this" (?) corrupt
> > memory used by the stack?
> 
> On an s3 resume, memory the OS may be using must not be changed by the
> bios.  When bochs bios detects an s3 resume, it jumps to s3_post with
> the stack pointer set to 0xfffe.  In s3_post, there are "call"
> instruction which will alter memory at 0xfffe (to store the return
> address).  This could break the resume, because the OS could be using
> that memory for something else.
> 
> Gleb is suggesting that we change that to 0xffe, because the OS can't
> be using memory at that address and expect s3 resume to work.  (The
> first 4KiB is reserved for BIOS use.)
> 
And the patch I've sent set sp to 0xffe only on S3 resume path where
stack usage is minimal.

--
			Gleb.

[Qemu-devel] Re: [Bochs-developers] [PATCH v5 1/5] Add S3 state to DSDT.Handle resume event in the BIOS.

[Sebastian Herbszt]

Gleb Natapov wrote:
> On Sat, Dec 06, 2008 at 09:57:38PM -0500, Kevin O'Connor wrote:
>> Also, wouldn't this corrupt memory used by the stack (the stack gets
>> set to 0xfffe, and s3_post has call insns in it)?
> Here is the patch to set stack pointer to a different value on S3 resume:
> 
> Signed-off-by: Gleb Natapov <gleb@redhat.com>
> 
> diff --git a/bios/rombios.c b/bios/rombios.c
> index 7a9c1fd..8e1d3ec 100644
> --- a/bios/rombios.c
> +++ b/bios/rombios.c
> @@ -9114,6 +9114,7 @@ retf_post_0x467:
>   retf
> 
> s3_post:
> +  mov sp, #0xffe
> #if BX_ROMBIOS32
>   call rombios32_init
> #endif

Stanislav, please apply.

- Sebastian