From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L8B4e-0000X9-UW for qemu-devel@nongnu.org; Thu, 04 Dec 2008 05:04:44 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L8B4e-0000Wr-9r for qemu-devel@nongnu.org; Thu, 04 Dec 2008 05:04:44 -0500 Received: from [199.232.76.173] (port=48814 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L8B4e-0000Wo-0E for qemu-devel@nongnu.org; Thu, 04 Dec 2008 05:04:44 -0500 Received: from mail.gmx.net ([213.165.64.20]:49202) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1L8B4c-00069Y-Uo for qemu-devel@nongnu.org; Thu, 04 Dec 2008 05:04:43 -0500 Message-ID: <4937AB37.2020207@gmx.net> Date: Thu, 04 Dec 2008 11:04:39 +0100 From: Carl-Daniel Hailfinger MIME-Version: 1.0 Subject: Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 ACPI state (suspend to memory) in BIOS References: <20081127110220.25353.83454.stgit@dhcp-1-237.tlv.redhat.com> <492E8FCC.2020203@gmx.net> <20081127123557.GB21985@redhat.com> <000301c950c2$4e2058b0$ea610a10$@com> <492EEFF8.50802@gmx.net> <000001c950cb$57f35dc0$07da1940$@com> <492F0B69.6080407@gmx.net> <000c01c9525a$a3325990$e9970cb0$@com> In-Reply-To: <000c01c9525a$a3325990$e9970cb0$@com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: bochs-developers@lists.sourceforge.net On 29.11.2008 20:42, Stanislav wrote: > Again, I mean Bochs doesn't emulate caches. So what do you mean by catchall > emulation ? > To allocate kind of dummy 32K block and use it when CRAM mode and delete > immediately after ? > Yes, exactly. However, the size of the dummy block depends on your cache size. And I have seen Intel CPUs (with 2 MB cache) which used up to 1056 kB of cache during CAR mode. > About the way you enable CRAM mode - it would be nice if we agree to use a > protocol which real hardware needs. > Yes. That is my goal. The problem is that CPU documentation is often a bit ambiguous about how CAR mode is enabled. AFAIK the common denominator is the CARsize <= Cachesize setting. That is really unusual for any point in time (during OS execution) except for the short time where CAR is enabled in the firmware/BIOS. > I still hope to be able to execute real hardware BIOSes on Bochs for example > That would be cool. The RAM controller emulation may need some tweaking, though. Regards, Carl-Daniel > Stanislav > > -----Original Message----- > From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] > Sent: Thursday, November 27, 2008 11:05 PM > To: qemu-devel@nongnu.org > Cc: bochs-developers@lists.sourceforge.net > Subject: Re: [Bochs-developers] [Qemu-devel] [PATCH v5 0/5] Support for S3 > ACPI state (suspend to memory) in BIOS > > On 27.11.2008 21:04, Stanislav wrote: > >> What is the catchall emulation ? Could you explain/point me some docs ? >> >> > > Sorry, it was only a brief sentence. Basically, if the total size of all > cached areas is not bigger than CPU cache size, no cache line will be > evicted and the cache behaves like Cache-as-RAM (CAR). That should be > doable in Bochs, KVM and Qemu. > > Or were you looking for BIOS code to enable CAR? That is indeed > processor specific, but any of the existing CAR implementations will > work if the catchall emulation is used. > > Regards, > Carl-Daniel > > -- http://www.hailfinger.org/