From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L9QiH-0006Zp-M1 for qemu-devel@nongnu.org; Sun, 07 Dec 2008 15:58:49 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L9QiF-0006XJ-Kv for qemu-devel@nongnu.org; Sun, 07 Dec 2008 15:58:48 -0500 Received: from [199.232.76.173] (port=51039 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L9QiF-0006Ww-Cf for qemu-devel@nongnu.org; Sun, 07 Dec 2008 15:58:47 -0500 Received: from smtp7-g19.free.fr ([212.27.42.64]:38331) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L9QiE-00059T-E2 for qemu-devel@nongnu.org; Sun, 07 Dec 2008 15:58:47 -0500 Received: from smtp7-g19.free.fr (localhost [127.0.0.1]) by smtp7-g19.free.fr (Postfix) with ESMTP id 78B0EB0166 for ; Sun, 7 Dec 2008 21:58:44 +0100 (CET) Received: from [192.168.0.32] (rob92-10-88-171-126-33.fbx.proxad.net [88.171.126.33]) by smtp7-g19.free.fr (Postfix) with ESMTP id 4DF4EB0148 for ; Sun, 7 Dec 2008 21:58:43 +0100 (CET) Message-ID: <493C3902.4010105@reactos.org> Date: Sun, 07 Dec 2008 21:58:42 +0100 From: =?ISO-8859-1?Q?Herv=E9_Poussineau?= MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------070409030409070309090805" Subject: [Qemu-devel] [RESEND][PATCH] Fix memory-mapped i8042 on MIPS Magnum Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------070409030409070309090805 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Hi, Current implementation of memory-mapped i8042 controller is atm=20 implemented with an interface shift (it_shift) parameter, like most all=20 memory-mapped devices in Qemu. However, this isn't suitable for MIPS Magnum, where i8042 controller is=20 at 0x80005000 up to 0x80005fff. Thomas Bogendoerfer (from #mipslinux) tested the behaviour of a real=20 machine, and found that odd addresses are for status/command register,=20 and even addresses for data register. Attached patch implements this behaviour by replacing the it_shift=20 parameter by a mask one. Incidentally, keyboard now works on OpenBSD 2.3, which accesses i8042=20 controller at 0x80005060 and 0x80005061. Signed-off-by: Herv=E9 Poussineau Changes since v1: - updated to qemu svn Herv=E9 --------------070409030409070309090805 Content-Type: plain/text; name="pckbd_mm_v2.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="pckbd_mm_v2.diff" Index: hw/mips_jazz.c =================================================================== --- hw/mips_jazz.c (revision 5917) +++ hw/mips_jazz.c (working copy) @@ -229,7 +229,7 @@ cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); /* Keyboard (i8042) */ - i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0); + i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); /* Serial ports */ if (serial_hds[0]) Index: hw/pc.h =================================================================== --- hw/pc.h (revision 5917) +++ hw/pc.h (working copy) @@ -71,7 +71,7 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, - target_phys_addr_t base, int it_shift); + target_phys_addr_t base, ram_addr_t size, ram_addr_t mask); /* mc146818rtc.c */ Index: hw/pckbd.c =================================================================== --- hw/pckbd.c (revision 5917) +++ hw/pckbd.c (working copy) @@ -125,7 +125,7 @@ qemu_irq irq_kbd; qemu_irq irq_mouse; - int it_shift; + ram_addr_t mask; } KBDState; static KBDState kbd_state; @@ -391,28 +391,20 @@ { KBDState *s = opaque; - switch (addr >> s->it_shift) { - case 0: - return kbd_read_data(s, 0) & 0xff; - case 1: + if (addr & s->mask) return kbd_read_status(s, 0) & 0xff; - default: - return 0xff; - } + else + return kbd_read_data(s, 0) & 0xff; } static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) { KBDState *s = opaque; - switch (addr >> s->it_shift) { - case 0: - kbd_write_data(s, 0, value & 0xff); - break; - case 1: + if (addr & s->mask) kbd_write_command(s, 0, value & 0xff); - break; - } + else + kbd_write_data(s, 0, value & 0xff); } static CPUReadMemoryFunc *kbd_mm_read[] = { @@ -428,19 +420,19 @@ }; void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, - target_phys_addr_t base, int it_shift) + target_phys_addr_t base, ram_addr_t size, ram_addr_t mask) { KBDState *s = &kbd_state; int s_io_memory; s->irq_kbd = kbd_irq; s->irq_mouse = mouse_irq; - s->it_shift = it_shift; + s->mask = mask; kbd_reset(s); register_savevm("pckbd", 0, 3, kbd_save, kbd_load, s); s_io_memory = cpu_register_io_memory(0, kbd_mm_read, kbd_mm_write, s); - cpu_register_physical_memory(base, 2 << it_shift, s_io_memory); + cpu_register_physical_memory(base, size, s_io_memory); s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); --------------070409030409070309090805--