From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LF8SO-0007d8-Bz for qemu-devel@nongnu.org; Tue, 23 Dec 2008 09:42:00 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LF8SN-0007cq-SK for qemu-devel@nongnu.org; Tue, 23 Dec 2008 09:42:00 -0500 Received: from [199.232.76.173] (port=59645 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LF8SN-0007cn-NE for qemu-devel@nongnu.org; Tue, 23 Dec 2008 09:41:59 -0500 Received: from pop-tawny.atl.sa.earthlink.net ([207.69.195.67]:64957) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LF8SN-0007P6-A8 for qemu-devel@nongnu.org; Tue, 23 Dec 2008 09:41:59 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=[192.168.0.90]) by pop-tawny.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1LF8SK-0007DR-00 for qemu-devel@nongnu.org; Tue, 23 Dec 2008 09:41:56 -0500 Message-ID: <4950F8B2.1030109@earthlink.net> Date: Tue, 23 Dec 2008 09:41:54 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------060404040808000209090002" Subject: [Qemu-devel] [PATCH] better SuperSPARC emulation Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------060404040808000209090002 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Add better SuperSPARC processor emulation. With this patch, openboot is able to detect the SuperSPARC processor revision and cache size properly. --------------060404040808000209090002 Content-Type: text/plain; name="supersparc.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="supersparc.diff.txt" Index: target-sparc/helper.c =================================================================== --- target-sparc/helper.c (revision 6121) +++ target-sparc/helper.c (working copy) @@ -688,6 +688,7 @@ #if !defined(TARGET_SPARC64) env->mmuregs[0] |= def->mmu_version; cpu_sparc_set_id(env, 0); + env->mxccregs[7] |= def->mxcc_version; #else env->mmu_version = def->mmu_version; env->maxtl = def->maxtl; @@ -972,19 +973,6 @@ CPU_FEATURE_FSMULD, }, { - .name = "TI SuperSparc II", - .iu_version = 0x40000000, - .fpu_version = 0 << 17, - .mmu_version = 0x04000000, - .mmu_bm = 0x00002000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x0000ffff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, - }, - { .name = "TI MicroSparc I", .iu_version = 0x41000000, .fpu_version = 4 << 17, @@ -1027,9 +1015,9 @@ }, { .name = "TI SuperSparc 40", // STP1020NPGA - .iu_version = 0x41000000, + .iu_version = 0x41000000, // SuperSPARC 2.x .fpu_version = 0 << 17, - .mmu_version = 0x00000000, + .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC .mmu_bm = 0x00002000, .mmu_ctpr_mask = 0xffffffc0, .mmu_cxr_mask = 0x0000ffff, @@ -1040,9 +1028,9 @@ }, { .name = "TI SuperSparc 50", // STP1020PGA - .iu_version = 0x40000000, + .iu_version = 0x40000000, // SuperSPARC 3.x .fpu_version = 0 << 17, - .mmu_version = 0x04000000, + .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC .mmu_bm = 0x00002000, .mmu_ctpr_mask = 0xffffffc0, .mmu_cxr_mask = 0x0000ffff, @@ -1053,22 +1041,23 @@ }, { .name = "TI SuperSparc 51", - .iu_version = 0x43000000, + .iu_version = 0x40000000, // SuperSPARC 3.x .fpu_version = 0 << 17, - .mmu_version = 0x04000000, + .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC .mmu_bm = 0x00002000, .mmu_ctpr_mask = 0xffffffc0, .mmu_cxr_mask = 0x0000ffff, .mmu_sfsr_mask = 0xffffffff, .mmu_trcr_mask = 0xffffffff, + .mxcc_version = 0x00000104, .nwindows = 8, .features = CPU_DEFAULT_FEATURES, }, { .name = "TI SuperSparc 60", // STP1020APGA - .iu_version = 0x40000000, + .iu_version = 0x40000000, // SuperSPARC 3.x .fpu_version = 0 << 17, - .mmu_version = 0x03000000, + .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC .mmu_bm = 0x00002000, .mmu_ctpr_mask = 0xffffffc0, .mmu_cxr_mask = 0x0000ffff, @@ -1079,18 +1068,33 @@ }, { .name = "TI SuperSparc 61", - .iu_version = 0x44000000, + .iu_version = 0x44000000, // SuperSPARC 3.x .fpu_version = 0 << 17, - .mmu_version = 0x04000000, + .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC .mmu_bm = 0x00002000, .mmu_ctpr_mask = 0xffffffc0, .mmu_cxr_mask = 0x0000ffff, .mmu_sfsr_mask = 0xffffffff, .mmu_trcr_mask = 0xffffffff, + .mxcc_version = 0x00000104, .nwindows = 8, .features = CPU_DEFAULT_FEATURES, }, { + .name = "TI SuperSparc II", + .iu_version = 0x40000000, // SuperSPARC II 1.x + .fpu_version = 0 << 17, + .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC + .mmu_bm = 0x00002000, + .mmu_ctpr_mask = 0xffffffc0, + .mmu_cxr_mask = 0x0000ffff, + .mmu_sfsr_mask = 0xffffffff, + .mmu_trcr_mask = 0xffffffff, + .mxcc_version = 0x00000104, + .nwindows = 8, + .features = CPU_DEFAULT_FEATURES, + }, + { .name = "Ross RT625", .iu_version = 0x1e000000, .fpu_version = 1 << 17, Index: target-sparc/cpu.h =================================================================== --- target-sparc/cpu.h (revision 6121) +++ target-sparc/cpu.h (working copy) @@ -210,6 +210,7 @@ uint32_t mmu_cxr_mask; uint32_t mmu_sfsr_mask; uint32_t mmu_trcr_mask; + uint32_t mxcc_version; uint32_t features; uint32_t nwindows; uint32_t maxtl; --------------060404040808000209090002--