[Qemu-devel] [PATCH] MIPS CP0 Random register fix

[Qemu-devel] [PATCH] MIPS CP0 Random register fix

[Hervé Poussineau]

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Hello,

MIPS TLBWR instruction asks the CPU to randomly overwrite a TLB entry by 
the one we want to write. The TLB index needs to be between number of 
wired TLB entries and TLB count - 1.
However, algorithm to choose which one to overwrite is implementation 
dependant.

At the moment, Qemu implementation is a random one, but can return the 
same value more than once.
Due to this, NetBSD 1.6.2 on MIPS Magnum emulation crashes.

After checking MIPS CPU documentations, multiple algorithms exist to 
update this Random register, but they all guarantee that 2 close TLBWR 
instructions don't overwrite the same TLB.

Attached patch prevents returning the same TLB index twice, by choosing 
the next immediate value if random value is the same as before.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Hervé

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Re: [Qemu-devel] [PATCH] MIPS CP0 Random register fix

[Aurelien Jarno]

On Sat, Jan 03, 2009 at 06:20:13PM +0100, Hervé Poussineau wrote:
> Hello,
>
> MIPS TLBWR instruction asks the CPU to randomly overwrite a TLB entry by  
> the one we want to write. The TLB index needs to be between number of  
> wired TLB entries and TLB count - 1.
> However, algorithm to choose which one to overwrite is implementation  
> dependant.
>
> At the moment, Qemu implementation is a random one, but can return the  
> same value more than once.
> Due to this, NetBSD 1.6.2 on MIPS Magnum emulation crashes.
>
> After checking MIPS CPU documentations, multiple algorithms exist to  
> update this Random register, but they all guarantee that 2 close TLBWR  
> instructions don't overwrite the same TLB.
>
> Attached patch prevents returning the same TLB index twice, by choosing  
> the next immediate value if random value is the same as before.

I have actually applied a different patch, which also change to a better
random generator. PLease confirm that it works.

-- 
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