qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits
Date: Mon, 29 Jul 2019 18:30:42 -0700	[thread overview]
Message-ID: <4962c208-04d6-65e8-556d-b1805f4e4ebf@linaro.org> (raw)
In-Reply-To: <CAFEAcA-+PfEMDE9QJZJ+_yqV0KYY6ih2yxA8c_w1bmrz7GtUkA@mail.gmail.com>

On 7/29/19 6:43 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:50, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> With this, we can have the function return a value from the DisasContext.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  scripts/decodetree.py             | 5 ++++-
>>  tests/decode/succ_function.decode | 2 ++
>>  2 files changed, 6 insertions(+), 1 deletion(-)
>>  create mode 100644 tests/decode/succ_function.decode
>>
>> diff --git a/scripts/decodetree.py b/scripts/decodetree.py
>> index d7a59d63ac..4259d87a95 100755
>> --- a/scripts/decodetree.py
>> +++ b/scripts/decodetree.py
>> @@ -195,7 +195,10 @@ class MultiField:
>>      """Class representing a compound instruction field"""
>>      def __init__(self, subs, mask):
>>          self.subs = subs
>> -        self.sign = subs[0].sign
>> +        if len(subs):
>> +            self.sign = subs[0].sign
>> +        else:
>> +            self.sign = 0
>>          self.mask = mask
>>
>>      def __str__(self):
>> diff --git a/tests/decode/succ_function.decode b/tests/decode/succ_function.decode
>> new file mode 100644
>> index 0000000000..632a9de252
>> --- /dev/null
>> +++ b/tests/decode/succ_function.decode
>> @@ -0,0 +1,2 @@
>> +%foo  !function=foo
>> +foo   00000000000000000000000000000000 %foo
>> --
>> 2.17.1
> 
> Could you also update the documentation in docs/devel/decodetree.rst ?
> 
> This code change looks like it also now allows definitions
> of fields that specify nothing at all (ie there's no check
> that a field definition with no "unnamed_field" parts has
> a !function specifier) -- what do they do, or should they
> be made syntax errors ?

Ah good point.  Should be syntax errors.

> Is one of these functions which just returns a constant
> from no input bits still a "static int func(DisasContext *s, int x)"
> taking a pointless input argument, or is it now a
> "static int func(DisasContext *s)" ? I guess from the fact
> this code doesn't change the way a call is output that it
> is the former, but would the latter be cleaner ?

Right on both counts.  Because of how the loop in MultiField is set up, x will
always be given 0.  I'll see about cleaning this up.

In the meantime, fyi, this is used for setting the S bit for thumb1 insns,
where S=0 iff the insn is within an IT block.


r~


  reply	other threads:[~2019-07-30  1:31 UTC|newest]

Thread overview: 110+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits Richard Henderson
2019-07-29 13:43   ` Peter Maydell
2019-07-30  1:30     ` Richard Henderson [this message]
2019-07-26 17:49 ` [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn Richard Henderson
2019-07-29 13:48   ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn Richard Henderson
2019-07-29 13:50   ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn Richard Henderson
2019-07-29 13:52   ` Peter Maydell
2019-07-30  2:11     ` Richard Henderson
2019-08-06  9:55       ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address Richard Henderson
2019-07-29 13:54   ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read Richard Henderson
2019-07-29 14:05   ` Peter Maydell
2019-07-30  0:38     ` Richard Henderson
2019-08-06 10:00       ` Peter Maydell
2019-08-06 15:04         ` Richard Henderson
2019-08-06 15:21           ` Peter Maydell
2019-08-06 15:53             ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit Richard Henderson
2019-07-29 14:15   ` Peter Maydell
2019-07-30  0:51     ` Richard Henderson
2019-08-06  9:44       ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-07-29 14:26   ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg Richard Henderson
2019-07-29 14:27   ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless Richard Henderson
2019-07-29 14:32   ` Peter Maydell
2019-07-30  0:57     ` Richard Henderson
2019-07-30  8:49       ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-07-29 14:42   ` Peter Maydell
2019-08-06 21:41   ` Philippe Mathieu-Daudé
2019-08-08 11:41   ` Aleksandar Markovic
2019-08-08 15:43     ` Richard Henderson
2019-08-09 10:31       ` Aleksandar Markovic
2019-08-09 14:55         ` Richard Henderson
2019-08-09 15:30           ` Aleksandar Markovic
2019-07-26 17:49 ` [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op Richard Henderson
2019-07-29 14:44   ` Peter Maydell
2019-08-06 21:43   ` Philippe Mathieu-Daudé
2019-07-26 17:49 ` [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) Richard Henderson
2019-07-29 15:25   ` Peter Maydell
2019-07-30  1:25     ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-05 15:32   ` Peter Maydell
2019-08-05 16:20     ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-05 15:40   ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 39/67] target/arm: Convert SG Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 40/67] target/arm: Convert TT Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb Richard Henderson
2019-07-26 18:13   ` Peter Maydell
2019-07-26 18:34     ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i Richard Henderson
2019-07-26 18:40 ` [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-05 15:44 ` Peter Maydell
2019-08-05 21:26   ` Richard Henderson
2019-08-06 10:01     ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=4962c208-04d6-65e8-556d-b1805f4e4ebf@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=alex.bennee@linaro.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).