From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LPN8z-0003R0-Ix for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:24:17 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LPN8x-0003Oz-Rl for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:24:17 -0500 Received: from [199.232.76.173] (port=37352 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LPN8x-0003Om-J7 for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:24:15 -0500 Received: from mx2.redhat.com ([66.187.237.31]:44237) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LPN8x-0002yw-4w for qemu-devel@nongnu.org; Tue, 20 Jan 2009 15:24:15 -0500 Message-ID: <497632E1.3050707@redhat.com> Date: Tue, 20 Jan 2009 22:24:01 +0200 From: Avi Kivity MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 4/6] replace cpu_physical_memory_rw References: <1232477465-32386-1-git-send-email-glommer@redhat.com> <1232477465-32386-2-git-send-email-glommer@redhat.com> <1232477465-32386-3-git-send-email-glommer@redhat.com> <1232477465-32386-4-git-send-email-glommer@redhat.com> <1232477465-32386-5-git-send-email-glommer@redhat.com> In-Reply-To: <1232477465-32386-5-git-send-email-glommer@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com Glauber Costa wrote: > This patch introduces a kvm version of cpu_physical_memory_rw. > The main motivation is to bypass tcg version, which contains > tcg-specific code, as well as data structures not used by kvm, > such as l1_phys_map. > > In this patch, I'm using a runtime selection of which function > to call, but the mid-term goal is to use function pointers in > a way very close to which QEMUAccel used to be. > You will need to trivially adjust this for cpu_physical_memory_map(). You're still allocating the page descriptors, right? My feeling is that qemu could long term drop phys_ram_base and move to a slot based structure; most lookups will hit on the first access (the largest slot). The main motivation is to enable memory hotplug. Of course this shouldn't interfere with this patchset going in. -- Do not meddle in the internals of kernels, for they are subtle and quick to panic.