From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LRb5I-0000ah-50 for qemu-devel@nongnu.org; Mon, 26 Jan 2009 18:41:40 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LRb5F-0000Zf-Ua for qemu-devel@nongnu.org; Mon, 26 Jan 2009 18:41:39 -0500 Received: from [199.232.76.173] (port=41238 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LRb5F-0000ZS-N1 for qemu-devel@nongnu.org; Mon, 26 Jan 2009 18:41:37 -0500 Received: from mail.gmx.net ([213.165.64.20]:57961) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1LRb5F-0000h9-41 for qemu-devel@nongnu.org; Mon, 26 Jan 2009 18:41:37 -0500 Message-ID: <497E4A30.7070103@gmx.net> Date: Tue, 27 Jan 2009 00:41:36 +0100 From: Carl-Daniel Hailfinger MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] MTRR support on x86, part 2 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Anthony Liguori Load and save MTRR state together with machine state. Add support for the MTRRcap MSR which is used by the latest Bochs BIOS and some operating systems. Fix a typo in ext2_feature_name. With this patch, MTRR emulation should be good enough to not trigger any sanity checks in well behaved BIOS/kernel code. Some corner cases for BIOS/firmware usage remain to be implemented, but that can be deferred to another patch. Also, MTRR accesses on hardware not supporting MTRRs should cause #GP. That can be enforced by another patch as well. Signed-off-by: Carl-Daniel Hailfinger Index: target-i386/helper.c =================================================================== --- target-i386/helper.c (Revision 6461) +++ target-i386/helper.c (Arbeitskopie) @@ -55,7 +55,7 @@ }; static const char *ext2_feature_name[] = { "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", - "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", "mttr", "pge", "mca", "cmov", + "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", "mtrr", "pge", "mca", "cmov", "pat", "pse36", NULL, NULL /* Linux mp */, "nx" /* Intel xd */, NULL, "mmxext", "mmx", "fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp", NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow", }; Index: target-i386/machine.c =================================================================== --- target-i386/machine.c (Revision 6461) +++ target-i386/machine.c (Arbeitskopie) @@ -134,6 +134,15 @@ qemu_put_be16s(f, &env->intercept_dr_write); qemu_put_be32s(f, &env->intercept_exceptions); qemu_put_8s(f, &env->v_tpr); + + /* MTRRs */ + for(i = 0; i < 11; i++) + qemu_put_be64s(f, &env->mtrr_fixed[i]); + qemu_put_be64s(f, &env->mtrr_deftype); + for(i = 0; i < 8; i++) { + qemu_put_be64s(f, &env->mtrr_var[i].base); + qemu_put_be64s(f, &env->mtrr_var[i].mask); + } } #ifdef USE_X86LDOUBLE @@ -169,7 +178,7 @@ int32_t a20_mask; if (version_id != 3 && version_id != 4 && version_id != 5 - && version_id != 6 && version_id != 7) + && version_id != 6 && version_id != 7 && version_id != 8) return -EINVAL; for(i = 0; i < CPU_NB_REGS; i++) qemu_get_betls(f, &env->regs[i]); @@ -302,6 +311,18 @@ qemu_get_be32s(f, &env->intercept_exceptions); qemu_get_8s(f, &env->v_tpr); } + + if (version_id >= 8) { + /* MTRRs */ + for(i = 0; i < 11; i++) + qemu_get_be64s(f, &env->mtrr_fixed[i]); + qemu_get_be64s(f, &env->mtrr_deftype); + for(i = 0; i < 8; i++) { + qemu_get_be64s(f, &env->mtrr_var[i].base); + qemu_get_be64s(f, &env->mtrr_var[i].mask); + } + } + /* XXX: ensure compatiblity for halted bit ? */ /* XXX: compute redundant hflags bits */ env->hflags = hflags; Index: target-i386/cpu.h =================================================================== --- target-i386/cpu.h (Revision 6461) +++ target-i386/cpu.h (Arbeitskopie) @@ -251,6 +251,11 @@ #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_MTRRcap 0xfe +#define MSR_MTRRcap_VCNT 8 +#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) +#define MSR_MTRRcap_WC_SUPPORTED (1 << 10) + #define MSR_IA32_SYSENTER_CS 0x174 #define MSR_IA32_SYSENTER_ESP 0x175 #define MSR_IA32_SYSENTER_EIP 0x176 Index: target-i386/op_helper.c =================================================================== --- target-i386/op_helper.c (Revision 6461) +++ target-i386/op_helper.c (Arbeitskopie) @@ -3215,6 +3215,13 @@ case MSR_MTRRdefType: val = env->mtrr_deftype; break; + case MSR_MTRRcap: + if (env->cpuid_features & CPUID_MTRR) + val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT | MSR_MTRRcap_WC_SUPPORTED; + else + /* XXX: exception ? */ + val = 0; + break; default: /* XXX: exception ? */ val = 0; -- http://www.hailfinger.org/