From: Jan Kiszka <jan.kiszka@siemens.com>
To: qemu-devel <qemu-devel@nongnu.org>
Subject: [Qemu-devel] [PATCH] arm: Fix gic_irq_state.level bitfield type
Date: Mon, 16 Feb 2009 12:30:14 +0100 [thread overview]
Message-ID: <49994E46.1030802@siemens.com> (raw)
Found while cleaning up compiler warnings: GIC_*_LEVEL macros strongly
suggest that gic_irq_state.level is intended to be per-CPU and not just
a single, global bit. I'm unable to test the effect, but it seems to be
the most reasonable fix for the apparent brokenness.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
hw/arm_gic.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index fef3113..8e61b6e 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -39,7 +39,7 @@ typedef struct gic_irq_state
unsigned enabled:1;
unsigned pending:NCPU;
unsigned active:NCPU;
- unsigned level:1;
+ unsigned level:NCPU;
unsigned model:1; /* 0 = N:N, 1 = 1:N */
unsigned trigger:1; /* nonzero = edge triggered. */
} gic_irq_state;
reply other threads:[~2009-02-16 11:30 UTC|newest]
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